Refactor Analog ports for compositional passive (#463)

First step and example plan for #114, to move single-circuit ports to a
compositional instead of inheritance model. This changes AnalogSink,
AnalogSource to have an internal `net` sub-port, which is the actual
net.

Introduces an infrastructural HasPassivePort, which effectively fulfills
the same function as (inheritance-based) CirucitPort, but with
composition.

Footprints implicitly understand HasPassivePort and automatically
connect the internal net.

For netlister net naming, the interior net name of ports is pruned out.

Refactors all the adapt_to(Analog*) to create the fully-defined Analog*
port in the wrapper, then connect its net to the internal passive-typed
port. The leftover adapt_to(Analog*) cases are adapting within a block
(eg, to connect to a peer-level sub-block) and cannot be removed. This
probably forms the new recommended practice.

Future PRs:
- Refactor other single-circuit ports
- Migrate uses to get rid of adapt_to
- Remove netlister blocks (NetBlock, CircuitPort, CircuitLink,
CircuitPortBridge) and refactor use sites
- Fully make Passive replace CircuitPort

Author: ducky64

edg/abstract_parts/AbstractAnalogSwitch.py

@@ -129,14 +129,12 @@ def __init__(self) -> None:
         self.control = self.Export(self.device.control)
 
         self.inputs = self.Port(Vector(AnalogSink.empty()))
-        self.out = self.Export(
-            self.device.com.adapt_to(
-                AnalogSource(
-                    voltage_out=self.inputs.hull(lambda x: x.link().voltage),
-                    signal_out=self.inputs.hull(lambda x: x.link().signal),
-                    current_limits=self.device.analog_current_limits,  # this device only, current draw propagated
-                    impedance=self.device.analog_on_resistance + self.inputs.hull(lambda x: x.link().source_impedance),
-                )
+        self.out = self.Port(
+            AnalogSource(
+                voltage_out=self.inputs.hull(lambda x: x.link().voltage),
+                signal_out=self.inputs.hull(lambda x: x.link().signal),
+                current_limits=self.device.analog_current_limits,  # this device only, current draw propagated
+                impedance=self.device.analog_on_resistance + self.inputs.hull(lambda x: x.link().source_impedance),
             )
         )
 
@@ -145,18 +143,20 @@ def __init__(self) -> None:
     @override
     def generate(self) -> None:
         super().generate()
+
+        self.connect(self.out.net, self.device.com)
+
         self.inputs.defined()
         for elt in self.get(self.inputs.requested()):
-            self.connect(
-                self.inputs.append_elt(AnalogSink.empty(), elt),
-                self.device.inputs.request(elt).adapt_to(
-                    AnalogSink(
-                        voltage_limits=self.device.analog_voltage_limits,  # this device only, voltages propagated
-                        current_draw=self.out.link().current_drawn,
-                        impedance=self.out.link().sink_impedance + self.device.analog_on_resistance,
-                    )
+            input = self.inputs.append_elt(
+                AnalogSink(
+                    voltage_limits=self.device.analog_voltage_limits,  # this device only, voltages propagated
+                    current_draw=self.out.link().current_drawn,
+                    impedance=self.out.link().sink_impedance + self.device.analog_on_resistance,
                 ),
+                elt,
             )
+            self.connect(input.net, self.device.inputs.request(elt))
             if self.get(self.control_gnd.is_connected()):
                 self.connect(self.control_gnd, self.device.control_gnd)
 
@@ -182,13 +182,11 @@ def __init__(self) -> None:
         self.control = self.Export(self.device.control)
 
         self.outputs = self.Port(Vector(AnalogSource.empty()))
-        self.input = self.Export(
-            self.device.com.adapt_to(
-                AnalogSink(
-                    voltage_limits=self.device.analog_voltage_limits,  # this device only, voltages propagated
-                    current_draw=self.outputs.hull(lambda x: x.link().current_drawn),
-                    impedance=self.device.analog_on_resistance + self.outputs.hull(lambda x: x.link().sink_impedance),
-                )
+        self.input = self.Port(
+            AnalogSink(
+                voltage_limits=self.device.analog_voltage_limits,  # this device only, voltages propagated
+                current_draw=self.outputs.hull(lambda x: x.link().current_drawn),
+                impedance=self.device.analog_on_resistance + self.outputs.hull(lambda x: x.link().sink_impedance),
             )
         )
 
@@ -197,19 +195,21 @@ def __init__(self) -> None:
     @override
     def generate(self) -> None:
         super().generate()
+
+        self.connect(self.input.net, self.device.com)
+
         self.outputs.defined()
         for elt in self.get(self.outputs.requested()):
-            self.connect(
-                self.outputs.append_elt(AnalogSource.empty(), elt),
-                self.device.inputs.request(elt).adapt_to(
-                    AnalogSource(
-                        voltage_out=self.input.link().voltage,
-                        signal_out=self.input.link().signal,
-                        current_limits=self.device.analog_current_limits,  # this device only, voltages propagated
-                        impedance=self.input.link().source_impedance + self.device.analog_on_resistance,
-                    )
+            output = self.outputs.append_elt(
+                AnalogSource(
+                    voltage_out=self.input.link().voltage,
+                    signal_out=self.input.link().signal,
+                    current_limits=self.device.analog_current_limits,  # this device only, voltages propagated
+                    impedance=self.input.link().source_impedance + self.device.analog_on_resistance,
                 ),
+                elt,
             )
+            self.connect(output.net, self.device.inputs.request(elt))
 
     def demux_to(
         self, input: Optional[Port[AnalogLink]] = None, outputs: Optional[List[Port[AnalogLink]]] = None

edg/abstract_parts/AbstractCapacitor.py

@@ -403,10 +403,12 @@ def __init__(self, capacitance: RangeLike, *, exact_capacitance: BoolLike = Fals
         super().__init__()
 
         self.cap = self.Block(Capacitor(capacitance, voltage=RangeExpr(), exact_capacitance=exact_capacitance))
-        self.gnd = self.Export(self.cap.neg.adapt_to(Ground()), [Common])
-        self.io = self.Export(self.cap.pos.adapt_to(AnalogSink()), [InOut])  # ideal open port
+        self.gnd = self.Port(Ground.empty(), [Common])
+        self.io = self.Port(AnalogSink(), [InOut])  # ideal open port
 
         self.assign(self.cap.voltage, self.io.link().voltage - self.gnd.link().voltage)
+        self.connect(self.cap.neg.adapt_to(Ground()), self.gnd)  # TODO refactor #114
+        self.connect(self.io.net, self.cap.pos)
 
     def connected(
         self, gnd: Optional[Port[GroundLink]] = None, io: Optional[Port[AnalogLink]] = None

edg/abstract_parts/AbstractDiodes.py

@@ -1,9 +1,7 @@
-from typing import Dict, Any
+from typing import Dict
 from deprecated import deprecated
-from typing_extensions import override
 
 from ..electronics_model import *
-from .DummyDevices import ForcedAnalogVoltage
 from .Categories import *
 from .PartsTable import PartsTableColumn, PartsTableRow
 from .PartsTablePart import PartsTableSelector
@@ -222,27 +220,22 @@ class AnalogClampZenerDiode(Protection, KiCadImportableBlock):
     def __init__(self, voltage: RangeLike):
         super().__init__()
 
-        self.signal_in = self.Port(AnalogSink.empty(), [Input])
-        self.signal_out = self.Port(AnalogSource.empty(), [Output])
-        self.gnd = self.Port(Ground.empty(), [Common])
-
-        self.voltage = self.ArgParameter(voltage)
-
-    @override
-    def contents(self) -> None:
-        super().contents()
+        self.diode = self.Block(ZenerDiode(zener_voltage=voltage))
 
-        self.diode = self.Block(ZenerDiode(zener_voltage=self.voltage))
-
-        self.forced = self.Block(
-            ForcedAnalogVoltage(
-                forced_voltage=self.signal_in.link().voltage.intersect(
+        self.gnd = self.Port(Ground.empty(), [Common])
+        self.signal_in = self.Port(AnalogSink(), [Input])
+        self.signal_out = self.Port(
+            AnalogSource(
+                voltage_out=self.signal_in.link().voltage.intersect(
                     self.gnd.link().voltage + (0, self.diode.actual_zener_voltage.upper())
-                )
-            )
+                ),
+                signal_out=self.signal_in.link().signal,
+            ),
+            [Output],
         )
-        self.connect(self.signal_in, self.forced.signal_in)
-        self.connect(self.signal_out, self.forced.signal_out, self.diode.cathode.adapt_to(AnalogSink()))
+        self.assign(self.signal_in.current_draw, self.signal_out.link().current_drawn)
+
+        self.connect(self.signal_in.net, self.signal_out.net, self.diode.cathode)
         self.connect(self.diode.anode.adapt_to(Ground()), self.gnd)
 
     @override

edg/abstract_parts/AbstractResistor.py

@@ -392,14 +392,21 @@ def __init__(
     ):
         super().__init__()
 
-        self.signal_in = self.Port(AnalogSink.empty(), [Input])
-        self.signal_out = self.Port(AnalogSource.empty(), [Output])
-
         self.clamp_target = self.ArgParameter(clamp_target)
         self.clamp_current = self.ArgParameter(clamp_current)
         self.protection_voltage = self.ArgParameter(protection_voltage)
         self.zero_out = self.ArgParameter(zero_out)
 
+        self.signal_in = self.Port(AnalogSink(), [Input])
+        self.signal_out = self.Port(
+            AnalogSource(
+                voltage_out=self.signal_in.link().voltage.intersect(self.clamp_target),
+                signal_out=self.signal_in.link().signal,
+                impedance=RangeExpr(),
+            ),
+            [Output],
+        )
+
     @override
     def contents(self) -> None:
         super().contents()
@@ -415,17 +422,9 @@ def contents(self) -> None:
                 )
             )
         )
-        self.connect(self.res.a.adapt_to(AnalogSink()), self.signal_in)
-        self.connect(
-            self.res.b.adapt_to(
-                AnalogSource(
-                    voltage_out=self.signal_in.link().voltage.intersect(self.clamp_target),
-                    signal_out=self.signal_in.link().signal,
-                    impedance=self.signal_in.link().source_impedance + self.res.actual_resistance,
-                )
-            ),
-            self.signal_out,
-        )
+        self.connect(self.res.a, self.signal_in.net)
+        self.connect(self.res.b, self.signal_out.net)
+        self.assign(self.signal_out.impedance, self.signal_in.link().source_impedance + self.res.actual_resistance)
 
     @override
     def symbol_pinning(self, symbol_name: str) -> Dict[str, Port]:

edg/abstract_parts/AbstractSolidStateRelay.py

@@ -111,14 +111,22 @@ def symbol_pinning(self, symbol_name: str) -> Dict[str, BasePort]:
     def __init__(self) -> None:
         super().__init__()
 
+        self.ic = self.Block(SolidStateRelay())
+
         self.signal = self.Port(DigitalSink.empty())
         self.gnd = self.Port(Ground.empty(), [Common])
 
         self.apull = self.Port(AnalogSink.empty())
-        self.ain = self.Port(AnalogSink.empty())
+        self.ain = self.Port(
+            AnalogSink(
+                voltage_limits=RangeExpr(),
+                impedance=RangeExpr(),
+            )
+        )
         self.aout = self.Port(AnalogSource.empty())
+        self.assign(self.ain.voltage_limits, self.apull.link().voltage + self.ic.load_voltage_limit)
+        self.assign(self.ain.impedance, self.aout.link().sink_impedance + self.ic.load_resistance)
 
-        self.ic = self.Block(SolidStateRelay())
         self.res = self.Block(
             Resistor(
                 resistance=(
@@ -134,15 +142,7 @@ def __init__(self) -> None:
         self.connect(self.res.a, self.ic.ledk)
         self.connect(self.res.b.adapt_to(Ground()), self.gnd)
 
-        self.connect(
-            self.ain,
-            self.ic.feta.adapt_to(
-                AnalogSink(
-                    voltage_limits=self.apull.link().voltage + self.ic.load_voltage_limit,
-                    impedance=self.aout.link().sink_impedance + self.ic.load_resistance,
-                )
-            ),
-        )
+        self.connect(self.ain.net, self.ic.feta)
         self.pull_merge = self.Block(MergedAnalogSource()).connected_from(
             self.apull,
             self.ic.fetb.adapt_to(

edg/abstract_parts/AbstractTestPoint.py

@@ -120,8 +120,8 @@ class AnalogTestPoint(BaseTypedTestPoint, Block):
 
     def __init__(self, *args: Any) -> None:
         super().__init__(*args)
-        self.io = self.Port(AnalogSink.empty(), [InOut])
-        self.connect(self.io, self.tp.io.adapt_to(AnalogSink()))
+        self.io: AnalogSink = self.Port(AnalogSink(), [InOut])
+        self.connect(self.io.net, self.tp.io)
 
     def connected(self, io: Port[AnalogLink]) -> "AnalogTestPoint":
         cast(Block, builder.get_enclosing_block()).connect(io, self.io)
@@ -135,7 +135,8 @@ class AnalogCoaxTestPoint(BaseRfTestPoint, Block):
 
     def __init__(self, *args: Any) -> None:
         super().__init__(*args)
-        self.io = self.Export(self.conn.sig.adapt_to(AnalogSink()), [InOut])
+        self.io: AnalogSink = self.Port(AnalogSink(), [InOut])
+        self.connect(self.io.net, self.conn.sig)
 
     def connected(self, io: Port[AnalogLink]) -> "AnalogCoaxTestPoint":
         cast(Block, builder.get_enclosing_block()).connect(io, self.io)

edg/abstract_parts/DummyDevices.py

@@ -113,25 +113,11 @@ def __init__(self, forced_voltage: RangeLike, forced_current: RangeLike) -> None
         self.pwr_out = self.Port(VoltageSource(voltage_out=forced_voltage), [Output])
 
 
-class ForcedAnalogVoltage(DummyDevice, NetBlock):
-    def __init__(self, forced_voltage: RangeLike = RangeExpr()) -> None:
-        super().__init__()
-
-        self.signal_in = self.Port(AnalogSink(current_draw=RangeExpr()), [Input])
-
-        self.signal_out = self.Port(
-            AnalogSource(voltage_out=forced_voltage, signal_out=self.signal_in.link().signal), [Output]
-        )
-
-        self.assign(self.signal_in.current_draw, self.signal_out.link().current_drawn)
-
-
-class ForcedAnalogSignal(KiCadImportableBlock, DummyDevice, NetBlock):
+class ForcedAnalogSignal(KiCadImportableBlock, DummyDevice):
     def __init__(self, forced_signal: RangeLike = RangeExpr()) -> None:
         super().__init__()
 
         self.signal_in = self.Port(AnalogSink(current_draw=RangeExpr()), [Input])
-
         self.signal_out = self.Port(
             AnalogSource(
                 voltage_out=self.signal_in.link().voltage,
@@ -142,6 +128,7 @@ def __init__(self, forced_signal: RangeLike = RangeExpr()) -> None:
         )
 
         self.assign(self.signal_in.current_draw, self.signal_out.link().current_drawn)
+        self.connect(self.signal_in.net, self.signal_out.net)
 
     @override
     def symbol_pinning(self, symbol_name: str) -> Dict[str, BasePort]:

edg/abstract_parts/IoController.py

@@ -1,12 +1,13 @@
 from itertools import chain
-from typing import List, Dict, Tuple, Type, Optional, Any
+from typing import List, Dict, Tuple, Type, Optional, Any, Union
 
 from deprecated import deprecated
 from typing_extensions import override
 
 from ..electronics_model import *
 from .PinMappable import AllocatedResource, PinMappable, PinMapUtil
 from .Categories import ProgrammableController
+from ..electronics_model.PassivePort import HasPassivePort
 
 
 @non_library
@@ -97,12 +98,12 @@ def _export_ios_from(self, inner: "BaseIoController", excludes: List[BasePort] =
     @staticmethod
     def _instantiate_from(
         ios: List[BasePort], allocations: List[AllocatedResource]
-    ) -> Tuple[Dict[str, CircuitPort], RangeExpr]:
+    ) -> Tuple[Dict[str, Union[CircuitPort, HasPassivePort]], RangeExpr]:
         """Given a mapping of port types to IO ports and allocated resources from PinMapUtil,
         instantiate vector elements (if a vector) or init the port model (if a port)
         for the allocated resources using their data model and return the pin mapping."""
         ios_by_type = {io.elt_type() if isinstance(io, Vector) else type(io): io for io in ios}
-        pinmap: Dict[str, CircuitPort] = {}
+        pinmap: Dict[str, Union[CircuitPort, HasPassivePort]] = {}
 
         ports_assigned = IdentitySet[Port]()
         io_current_draw_builder = RangeExpr._to_expr_type(RangeExpr.ZERO)
@@ -141,14 +142,14 @@ def _instantiate_from(
             # TODO: recurse into bundles, really needs a more unified way of handling current draw
 
             if isinstance(allocation.pin, str):
-                assert isinstance(io_port, CircuitPort)
+                assert isinstance(io_port, (CircuitPort, HasPassivePort))
                 pinmap[allocation.pin] = io_port
             elif allocation.pin is None:
-                assert isinstance(io_port, CircuitPort)  # otherwise discarded
+                assert isinstance(io_port, (CircuitPort, HasPassivePort))  # otherwise discarded
             elif isinstance(allocation.pin, dict):
                 for subport_name, (pin_name, pin_resource) in allocation.pin.items():
                     subport = getattr(io_port, subport_name)
-                    assert isinstance(subport, CircuitPort), f"bad sub-port {pin_name} {subport}"
+                    assert isinstance(subport, (CircuitPort, HasPassivePort)), f"bad sub-port {pin_name} {subport}"
                     pinmap[pin_name] = subport
             else:
                 raise NotImplementedError(f"unknown allocation pin type {allocation.pin}")
@@ -183,7 +184,7 @@ def _io_pinmap(self) -> PinMapUtil:
         """Implement me. Defines the assignable IO pinmaps."""
         raise NotImplementedError
 
-    def _make_pinning(self) -> Dict[str, CircuitPort]:
+    def _make_pinning(self) -> Dict[str, Union[CircuitPort, HasPassivePort]]:
         allocation_list = []
         for io_port in self._io_ports:
             if isinstance(io_port, Vector):  # derive Vector connections from requested

edg/abstract_parts/MergedBlocks.py

@@ -69,7 +69,7 @@ def connected_from(self, *ins: Port[DigitalLink]) -> "MergedDigitalSource":
         return self
 
 
-class MergedAnalogSource(KiCadImportableBlock, DummyDevice, NetBlock, GeneratorBlock):
+class MergedAnalogSource(KiCadImportableBlock, DummyDevice, GeneratorBlock):
     @override
     def symbol_pinning(self, symbol_name: str) -> Dict[str, BasePort]:
         assert symbol_name.startswith("edg_importable:Merge")  # can be any merge
@@ -89,10 +89,11 @@ def generate(self) -> None:
         super().generate()
         self.inputs.defined()
         for in_request in self.get(self.inputs.requested()):
-            self.inputs.append_elt(
+            elt_port = self.inputs.append_elt(
                 AnalogSink(current_draw=self.output.link().current_drawn, impedance=self.output.link().sink_impedance),
                 in_request,
             )
+            self.connect(self.output.net, elt_port.net)
 
         self.assign(self.output.voltage_out, self.inputs.hull(lambda x: x.link().voltage))
         self.assign(self.output.signal_out, self.inputs.hull(lambda x: x.link().signal))