Example boards layout and library fixes

edg/circuits/DigitalAmplifiers.py

@@ -5,6 +5,55 @@
 from ..abstract_parts import *
 
 
+class LoadSwitch(PowerSwitch, Block):
+    """A high-side PMOS load switch, for when Vcontrol = Vout. The switch conducts when the control voltage
+    is low, and blocking when the control voltage is high.
+
+    Blocks in the forward direction only, uncontrolled reverse conduction is possible via the body diode.
+
+    This wraps a single PMOS device and provides higher-level electrical modeling."""
+
+    def __init__(
+        self,
+        max_rds: FloatLike = 1 * Ohm,
+        frequency: RangeLike = RangeExpr.ZERO,
+    ) -> None:
+        super().__init__()
+        self.max_rds = self.ArgParameter(max_rds)
+        self.frequency = self.ArgParameter(frequency)
+
+        self.gnd = self.Port(Ground(), [Common])  # not physically used, only as a standoff voltage reference
+        self.pwr_in = self.Port(VoltageSink(current_draw=RangeExpr()), [Power])
+
+        self.control = self.Port(DigitalSink(), [Input])
+        self.pwr_out = self.Port(VoltageSource(voltage_out=self.pwr_in.link().voltage), [Output])
+
+    @override
+    def contents(self) -> None:
+        super().contents()
+
+        self.fet = self.Block(
+            SwitchFet.PFet(
+                drain_voltage=self.pwr_in.link().voltage - self.gnd.link().voltage,
+                drain_current=self.pwr_out.link().current_drawn,
+                gate_voltage=self.control.link().voltage - self.gnd.link().voltage,
+                gate_threshold_voltage=(
+                    self.control.link().output_thresholds.lower() - self.gnd.link().voltage.lower(),
+                    self.control.link().output_thresholds.upper() - self.gnd.link().voltage.upper(),
+                ),
+                rds_on=(0, self.max_rds),
+                frequency=self.frequency,
+                drive_current=self.pwr_out.link().current_limits,
+            )
+        )
+
+        self.assign(self.pwr_in.current_draw, self.pwr_out.link().current_drawn)
+
+        self.connect(self.pwr_in.net, self.fet.source)
+        self.connect(self.control.net, self.fet.gate)
+        self.connect(self.pwr_out.net, self.fet.drain)
+
+
 class HighSideSwitch(PowerSwitch, KiCadSchematicBlock, GeneratorBlock):
     """A high-side FET switch, using a two switch architecture, a main pass PFET with a amplifier NFET to drive its gate.
     If clamp_voltage is nonzero, a zener clamp is generated to limit the PFET gate voltage.

edg/circuits/SwitchMatrix.py

@@ -80,12 +80,12 @@ def contents(self) -> None:
 @abstract_block_default(lambda: SwitchDiodeMatrix)
 class SwitchMatrix(InternalBlock, Block):
 
-    def __init__(self, nrows: IntLike, ncols: IntLike, voltage_drop: RangeLike = (0, 0.7) * Volt):
+    def __init__(self, ncols: IntLike, nrows: IntLike, voltage_drop: RangeLike = (0, 0.7) * Volt):
         super().__init__()
 
         self.voltage_drop = self.ArgParameter(voltage_drop)
-        self.nrows = self.ArgParameter(nrows)
         self.ncols = self.ArgParameter(ncols)
+        self.nrows = self.ArgParameter(nrows)
 
         self.rows = self.Port(Vector(DigitalSink.empty()))
         self.cols = self.Port(Vector(DigitalSource.empty()))
@@ -213,16 +213,16 @@ def __init__(self, *args: Any, **kwargs: Any) -> None:
     def generate(self) -> None:
         super().generate()
 
-        for row in range(self.get(self.nrows)):
-            self.rows.append_elt(DigitalSink.empty(), str(row))
+        for col in range(self.get(self.ncols)):
+            self.cols.append_elt(DigitalSource.empty(), str(col))
 
         self.sw = ElementDict[SwitchCell]()
-        for col in range(self.get(self.ncols)):
-            col_port = self.cols.append_elt(DigitalSource.empty(), str(col))
-            for row in range(self.get(self.nrows)):
+        for row in range(self.get(self.nrows)):
+            row_port = self.rows.append_elt(DigitalSink.empty(), str(row))
+            for col in range(self.get(self.ncols)):
                 cell = self.sw[f"{col},{row}"] = self.Block(SwitchCell(voltage_drop=self.voltage_drop))
-                self.connect(cell.col, col_port)
-                self.connect(cell.row, self.rows[str(row)])
+                self.connect(cell.col, self.cols[str(col)])
+                self.connect(cell.row, row_port)
 
         self.rows.defined()
         self.cols.defined()

edg/circuits/__init__.py

@@ -23,7 +23,7 @@
 from .ResistiveSensor import ConnectorResistiveSensor
 
 from .ControlCircuits import CompensatorType2
-from .DigitalAmplifiers import HighSideSwitch, OpenDrainDriver
+from .DigitalAmplifiers import LoadSwitch, HighSideSwitch, OpenDrainDriver
 
 from .I2cBitBang import I2cControllerBitBang
 from .I2cPullup import I2cPullup

edg/parts/analog/opamp/Ina219.py

@@ -1,3 +1,6 @@
+import warnings
+from typing import Any
+
 from typing_extensions import override
 
 from ....circuits import *
@@ -73,29 +76,49 @@ def generate(self) -> None:
         self.assign(self.actual_basic_part, False)
 
 
-class Ina219(CurrentSensor, Block):
-    """Current/voltage/power monitor with I2C interface"""
+class Ina219(CurrentSensor, GeneratorBlock):
+    """Bidirectional current/voltage/power monitor with I2C interface"""
 
-    def __init__(self, shunt_resistor: RangeLike = 2.0 * mOhm(tol=0.05), *, addr_lsb: IntLike = 0):
+    def __init__(
+        self, shunt_resistor: RangeLike = 2.0 * mOhm(tol=0.05), *, addr_lsb: IntLike = 0, flip_sense: BoolLike = False
+    ):
         super().__init__()
+        self.flip_sense = self.ArgParameter(flip_sense)
+        self.generator_param(self.flip_sense)
+
         self.ic = self.Block(Ina219_Device(addr_lsb))
         self.pwr = self.Export(self.ic.vs, [Power])
         self.gnd = self.Export(self.ic.gnd, [Common])
         self.i2c = self.Export(self.ic.i2c)
 
-        self.vs_cap = self.Block(DecouplingCapacitor(0.1 * uFarad(tol=0.2))).connected(self.gnd, self.pwr)
-
         self.Rs = self.Block(
             CurrentSenseResistor(
                 resistance=shunt_resistor,
             )
         )
 
-        self.sense_pos = self.Export(self.Rs.pwr_in)
-        self.sense_neg = self.Export(self.Rs.pwr_out)
+        self.sense_pwr_in = self.Export(self.Rs.pwr_in)
+        self.sense_pwr_out = self.Export(self.Rs.pwr_out)
 
     @override
-    def contents(self) -> None:
-        super().contents()
-        self.connect(self.Rs.sense_in, self.ic.in_pos)
-        self.connect(self.Rs.sense_out, self.ic.in_neg)
+    def generate(self) -> None:
+        super().generate()
+        self.vs_cap = self.Block(DecouplingCapacitor(0.1 * uFarad(tol=0.2))).connected(self.gnd, self.pwr)
+
+        if not self.get(self.flip_sense):
+            self.connect(self.Rs.sense_in, self.ic.in_pos)
+            self.connect(self.Rs.sense_out, self.ic.in_neg)
+        else:
+            self.connect(self.Rs.sense_in, self.ic.in_neg)
+            self.connect(self.Rs.sense_out, self.ic.in_pos)
+
+    def __getattr__(self, item: str) -> Any:
+        if item == "sense_pos":
+            warnings.warn(f"Use sense_pwr_in instead.", DeprecationWarning, stacklevel=2)
+            return self.sense_pwr_in
+        elif item == "sense_neg":
+            warnings.warn(f"Use sense_pwr_out instead.", DeprecationWarning, stacklevel=2)
+            return self.sense_pwr_out
+        else:
+            # ideally we'd use super().__getattr__(...), but that's not defined in base classes
+            raise AttributeError(item)

edg/parts/connector/Connectors.py

@@ -4,7 +4,7 @@
 from typing_extensions import override
 
 from ...circuits import *
-from .Headers import JstShSmHorizontal
+from .Jst import JstShSmHorizontal
 
 
 @abstract_block