From 9d66b4e1429069e072a8c22b9a47bdfa13e74d14 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Fri, 15 May 2026 23:58:48 -0700 Subject: [PATCH 1/3] inline typeOfPortLike, support export tap --- .../edg_ide/edgir_graph/ElkEdgirGraphUtils.scala | 12 ++++++++++-- .../edg_ide/swing/CompilerErrorTreeTableModel.scala | 2 +- .../scala/edg_ide/util/DesignFindDisconnected.scala | 2 +- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/src/main/scala/edg_ide/edgir_graph/ElkEdgirGraphUtils.scala b/src/main/scala/edg_ide/edgir_graph/ElkEdgirGraphUtils.scala index 177b279a..9ec7db02 100644 --- a/src/main/scala/edg_ide/edgir_graph/ElkEdgirGraphUtils.scala +++ b/src/main/scala/edg_ide/edgir_graph/ElkEdgirGraphUtils.scala @@ -4,10 +4,11 @@ import com.intellij.openapi.diagnostic.Logger import com.intellij.ui.JBColor import edg.EdgirUtils.SimpleLibraryPath import edg.compiler.{Compiler, RangeValue, TextValue} -import edg.wir.{BlockConnectivityAnalysis, DesignPath} +import edg.wir.DesignPath import edg_ide.util.EdgirAnalysisUtils import org.eclipse.elk.graph.{ElkGraphElement, ElkNode} import edgir.elem.elem +import edgir.ref.ref import java.awt.Color import scala.collection.mutable @@ -90,8 +91,15 @@ object ElkEdgirGraphUtils { type PropertyType = PortSide override val property: IProperty[PortSide] = PORT_SIDE + def typeOfPortLike(portLike: elem.PortLike): ref.LibraryPath = portLike.is match { + case elem.PortLike.Is.LibElem(lib) => lib + case elem.PortLike.Is.Port(port) => port.getSelfClass + case elem.PortLike.Is.Array(port) => port.getSelfClass + case other => throw new IllegalArgumentException(s"Unexpected PortLike ${other.getClass}") + } + def getSimplePortSide(port: PortWrapper): Option[PortSide] = { - val portType = BlockConnectivityAnalysis.typeOfPortLike(port.portLike) + val portType = typeOfPortLike(port.portLike) portType.toSimpleString match { case "Ground" => Some(PortSide.SOUTH) diff --git a/src/main/scala/edg_ide/swing/CompilerErrorTreeTableModel.scala b/src/main/scala/edg_ide/swing/CompilerErrorTreeTableModel.scala index 92e541e5..54da2dd7 100644 --- a/src/main/scala/edg_ide/swing/CompilerErrorTreeTableModel.scala +++ b/src/main/scala/edg_ide/swing/CompilerErrorTreeTableModel.scala @@ -50,7 +50,7 @@ object CompilerErrorNodeBase { case CompilerError.Unelaborated(ElaborateRecord.ParamValue(path), deps) => ("Unelaborated Param", path.toString, deps.toSeq.map(elaborateRecordToDetailNode)) case CompilerError.Unelaborated( - ElaborateRecord.Connect(toLinkPortPath, fromLinkPortPath, root), + ElaborateRecord.Connect(toLinkPortPath, fromLinkPortPath, root, tap), deps ) => ( diff --git a/src/main/scala/edg_ide/util/DesignFindDisconnected.scala b/src/main/scala/edg_ide/util/DesignFindDisconnected.scala index 05ec43ea..64a64924 100644 --- a/src/main/scala/edg_ide/util/DesignFindDisconnected.scala +++ b/src/main/scala/edg_ide/util/DesignFindDisconnected.scala @@ -40,7 +40,7 @@ object DesignFindDisconnected extends DesignBlockMap[(Seq[DesignPath], Seq[Strin .collect { // extract block side expr case expr.ValueExpr.Expr.Connected(expr.ConnectedExpr(Some(blockExpr), Some(linkExpr), _, _)) => blockExpr.expr - case expr.ValueExpr.Expr.Exported(expr.ExportedExpr(Some(exteriorExpr), Some(interiorExpr), _, _)) => + case expr.ValueExpr.Expr.Exported(expr.ExportedExpr(Some(exteriorExpr), Some(interiorExpr), false, _, _)) => interiorExpr.expr } .collect { // extract steps From a473506ca174df8d4a7592726888ff86247f69a6 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Sun, 17 May 2026 17:22:42 -0700 Subject: [PATCH 2/3] multinetlist generation --- PolymorphicBlocks | 2 +- .../runner/CompileProcessHandler.scala | 21 ++++++++++++++----- 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/PolymorphicBlocks b/PolymorphicBlocks index bb6e1f8d..cbe46eb3 160000 --- a/PolymorphicBlocks +++ b/PolymorphicBlocks @@ -1 +1 @@ -Subproject commit bb6e1f8d86445d787cea3f81a12bbbcddde417e0 +Subproject commit cbe46eb38689c221ca23539e64cfe42c0f6a388f diff --git a/src/main/scala/edg_ide/runner/CompileProcessHandler.scala b/src/main/scala/edg_ide/runner/CompileProcessHandler.scala index 83b5bff5..fb8242b6 100644 --- a/src/main/scala/edg_ide/runner/CompileProcessHandler.scala +++ b/src/main/scala/edg_ide/runner/CompileProcessHandler.scala @@ -430,13 +430,24 @@ class CompileProcessHandler( Map() ).mapErr(msg => s"while netlisting: $msg") .get - require(netlist.size == 1) Files.createDirectories(Paths.get(options.netlistFile).getParent) - val writer = new FileWriter(options.netlistFile, StandardCharsets.UTF_8) - writer.write(netlist.head._2) - writer.close() - f"wrote ${options.netlistFile}" + val writtenFiles = netlist.map { case (path, netlist) => + val filename = if (path == DesignPath()) { + options.netlistFile + } else { + if (options.netlistFile.endsWith(".net")) { + options.netlistFile.stripSuffix(".net") + "_" + path.toString.replace(',', '_') + ".net" + } else { + options.netlistFile + "_" + path.toString.replace(',', '_') + } + } + val writer = new FileWriter(filename, StandardCharsets.UTF_8) + writer.write(netlist) + writer.close() + filename + } + f"wrote ${writtenFiles.mkString(", ")}" } } else { console.print( From 59b16988e625c9acd2d90f152016687bbec6da09 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Sun, 17 May 2026 17:35:26 -0700 Subject: [PATCH 3/3] cleanup --- .../scala/edg_ide/edgir_graph/ElkEdgirGraphUtils.scala | 10 ++-------- .../scala/edg_ide/runner/CompileProcessHandler.scala | 4 ++-- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/src/main/scala/edg_ide/edgir_graph/ElkEdgirGraphUtils.scala b/src/main/scala/edg_ide/edgir_graph/ElkEdgirGraphUtils.scala index 9ec7db02..dcefb88a 100644 --- a/src/main/scala/edg_ide/edgir_graph/ElkEdgirGraphUtils.scala +++ b/src/main/scala/edg_ide/edgir_graph/ElkEdgirGraphUtils.scala @@ -5,6 +5,7 @@ import com.intellij.ui.JBColor import edg.EdgirUtils.SimpleLibraryPath import edg.compiler.{Compiler, RangeValue, TextValue} import edg.wir.DesignPath +import edg_ide.EdgirUtils.typeOfPortLike import edg_ide.util.EdgirAnalysisUtils import org.eclipse.elk.graph.{ElkGraphElement, ElkNode} import edgir.elem.elem @@ -91,15 +92,8 @@ object ElkEdgirGraphUtils { type PropertyType = PortSide override val property: IProperty[PortSide] = PORT_SIDE - def typeOfPortLike(portLike: elem.PortLike): ref.LibraryPath = portLike.is match { - case elem.PortLike.Is.LibElem(lib) => lib - case elem.PortLike.Is.Port(port) => port.getSelfClass - case elem.PortLike.Is.Array(port) => port.getSelfClass - case other => throw new IllegalArgumentException(s"Unexpected PortLike ${other.getClass}") - } - def getSimplePortSide(port: PortWrapper): Option[PortSide] = { - val portType = typeOfPortLike(port.portLike) + val portType = typeOfPortLike(port.portLike).get portType.toSimpleString match { case "Ground" => Some(PortSide.SOUTH) diff --git a/src/main/scala/edg_ide/runner/CompileProcessHandler.scala b/src/main/scala/edg_ide/runner/CompileProcessHandler.scala index fb8242b6..2126876f 100644 --- a/src/main/scala/edg_ide/runner/CompileProcessHandler.scala +++ b/src/main/scala/edg_ide/runner/CompileProcessHandler.scala @@ -432,7 +432,7 @@ class CompileProcessHandler( .get Files.createDirectories(Paths.get(options.netlistFile).getParent) - val writtenFiles = netlist.map { case (path, netlist) => + val writtenFiles = netlist.map { case (path, netlistData) => val filename = if (path == DesignPath()) { options.netlistFile } else { @@ -443,7 +443,7 @@ class CompileProcessHandler( } } val writer = new FileWriter(filename, StandardCharsets.UTF_8) - writer.write(netlist) + writer.write(netlistData) writer.close() filename }