@@ -7,25 +7,18 @@ UNISIMS_DIR = broken
77APP_NAME = marble
88GTX_TCL :=
99# Select between marblemini, marble, and marble_fiber
10+ # XXX needs support for marble_fiber
1011CONFIG ?= marblemini
1112ifeq ($(CONFIG ) ,marblemini)
12- CARRIER := marble1
1313 BOARD_DIR := marblemini
1414 BOARD_TOP_CSV := marble_mini_top.csv
15- XDC_FILTER :=
1615 IP_ADDR := 192.168.19.31
17- HWLOAD_CMD = openocd -f serial.cfg -f marble.cfg -c "transport select jtag; init; xc7_program xc7.tap; pld load 0 $(CONFIG ) .bit; exit"
18- HWTEST_EXTRA = $(PYTHON ) testcase.py -a $(IP_ADDR ) --trx --marble 0
1916else ifneq (,$(filter marble marble_fiber,$(CONFIG)))
20- CARRIER := marble2
2117 BOARD_DIR := marble
2218 BOARD_TOP_CSV := marble_top.csv
23- XDC_FILTER := | sed -e '/FMC._.[AK]_/s/IOSTANDARD LVCMOS25/IOSTANDARD LVCMOS25 PULLTYPE PULLUP/'
2419 SERIAL ?= ""
2520 IP_ADDR := 192.168.19.$(SERIAL )
2621 ZEST_SN ?= "LBNL DIGITIZER V1.0 SN 024"
27- HWLOAD_CMD = openocd -c "adapter driver ftdi; ftdi_serial 0000$(SERIAL ) ;" -f marble.cfg -c "transport select jtag; init; xc7_program xc7.tap; pld load 0 $(CONFIG ) .bit; exit"
28- HWTEST_EXTRA = $(PYTHON ) testcase.py -a $(IP_ADDR ) --trx --si570 && sn="$$($(PYTHON ) zest_sn.py -a $(IP_ADDR ) -p 803) " && echo "$$sn" && test "$$sn" = $(ZEST_SN )
2922 ifeq ($(CONFIG),marble_fiber)
3023 # XXX missing QSFP tcl
3124 GTX_TCL :=
@@ -91,7 +84,7 @@ scalar_marble_regmap.json: lb_marble_slave.v
9184marble_regmap.json : static_regmap.json scalar_marble_regmap.json
9285 $(PYTHON ) $(BUILD_DIR ) /merge_json.py -o $@ -i $(filter % .json, $^ )
9386config_romx.v : marble_regmap.json $(filter-out config_romx.v, $(MARBLE_SYNTH_SOURCE ) )
94- $(PYTHON ) -m leep.build_rom --placeholder_rev -v $@ -j $< -d " Marble Testing "
87+ $(PYTHON ) -m leep.build_rom --placeholder_rev -v $@ -j $< -d " $( CONFIG ) testing "
9588
9689# gen_features.py rules utilizing $(CONFIG)
9790$(APP_NAME ) _features : $(BUILD_DIR ) /gen_features.py marble_features.yaml
@@ -160,8 +153,12 @@ marble_base_yosys.json: marble_base_shell.v $(MARBLE_BASE_V0)
160153pin_map_fmc.csv : pin_map_fmc.py
161154 $(PYTHON ) $< > $@
162155
163- $(APP_NAME ) _$(CARRIER ) .xdc : $(BADGER_DIR ) /tests/meta-xdc.py $(patsubst % ,$(BOARD_SUPPORT_DIR ) /$(BOARD_DIR ) /% , Marble.xdc pin_map.csv) pin_map_fmc.csv $(BOARD_TOP_CSV )
164- $(PYTHON ) $^ $(XDC_FILTER ) > $@
156+ $(CONFIG ) .xdc : $(BADGER_DIR ) /tests/meta-xdc.py $(patsubst % ,$(BOARD_SUPPORT_DIR ) /$(BOARD_DIR ) /% , Marble.xdc pin_map.csv) pin_map_fmc.csv $(BOARD_TOP_CSV )
157+ ifeq ($(CONFIG ) ,marblemini)
158+ $(PYTHON) $^ > $@
159+ else
160+ $(PYTHON) $^ | sed -e '/FMC._.[AK]_/s/IOSTANDARD LVCMOS25/IOSTANDARD LVCMOS25 PULLTYPE PULLUP/' > $@
161+ endif
165162
166163# =====
167164# Initialization file for i2cbridge
@@ -185,11 +182,11 @@ Vmarble_base: $(MARBLE_BASE_V) fake_xadc.v marble_base_sim.cpp ethernet_model.c
185182# bitfile
186183MARBLE_SYNTH_SOURCE = marble_top.v tmds_test.v marble/gmii_clock_handle.v $(FPGA_FAMILY_DIR ) /xilinx/xilinx7_clocks.v gmii_to_rgmii.v $(MARBLE_BASE_V ) read_trx.dat ../../fpga_family/ds_clk_buf.v
187184
188- $(APP_NAME ) _ $( CARRIER ) .d : $(MARBLE_SYNTH_SOURCE ) $(APP_NAME ) _ $( CARRIER ) .xdc
185+ $(CONFIG ) .d : $(MARBLE_SYNTH_SOURCE ) $(CONFIG ) .xdc
189186 echo $^ | tr ' ' ' \n' > $@
190187
191- # Target is now $(CONFIG).bit (e.g. marblemini.bit or marble_fiber .bit)
192- $(CONFIG ) .bit : marble.tcl $(APP_NAME ) _ $( CARRIER ) .d $(APP_NAME ) _features bit_stamp_mod
188+ # Target is now $(CONFIG).bit (e.g. marblemini.bit or marble .bit)
189+ $(CONFIG ) .bit : marble.tcl $(CONFIG ) .d $(APP_NAME ) _features bit_stamp_mod
193190 $(SYNTH_VIVADO ) $< -tclargs $(filter % .d, $^ ) $(CONFIG ) $(APP_NAME ) $(BUILD_DIR ) /vivado_tcl/swap_gitid.tcl $(GTX_TCL )
194191
195192.PHONY : bit
@@ -200,14 +197,23 @@ bit: $(CONFIG).bit
200197
201198.PHONY : hwload hwtest
202199hwload :
203- @echo " Loading $( APP_NAME) .bit onto $( CONFIG) ..."
204- $(HWLOAD_CMD )
200+ @echo " Loading $( CONFIG) .bit onto $( CONFIG) ..."
201+ ifeq ($(CONFIG ) ,marblemini)
202+ openocd -f serial.cfg -f marble.cfg -c "transport select jtag; init; xc7_program xc7.tap; pld load 0 $(CONFIG).bit; exit"
203+ else
204+ openocd -c "adapter driver ftdi; ftdi_serial 0000$(SERIAL);" -f marble.cfg -c "transport select jtag; init; xc7_program xc7.tap; pld load 0 $(CONFIG).bit; exit"
205+ endif
205206
206207hwtest : udprtx
207208 ping -c 2 $(IP_ADDR )
208209 test $$(PYTHONPATH=../common $(PYTHON ) -m leep.cli leep://$(IP_ADDR ) :803 gitid ) = $$(git rev-parse HEAD ) && echo " gitid OK"
209210 ./udprtx $(IP_ADDR ) 100000 8 # should take under 3 seconds
210- $(HWTEST_EXTRA )
211+ ifeq ($(CONFIG ) ,marblemini)
212+ $(PYTHON) testcase.py -a $(IP_ADDR) --trx --marble 0
213+ else
214+ $(PYTHON) testcase.py -a $(IP_ADDR) --trx --si570
215+ sn="$$($(PYTHON) zest_sn.py -a $(IP_ADDR) -p 803)" && echo "$$sn" && test "$$sn" = $(ZEST_SN)
216+ endif
211217
212218dna_tb : dna_tb.v dna.v
213219
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