[Z80][GISel] Fix eZ80 s16 shift-by-const selection from o16 sources.

The eZ80 G_SHL selector path for s16 shifts by 2..6 was constraining the
source vreg to A16 before emitting:

  SUBREG_TO_REG
  COPY to UHL
  repeated ADD24aa
  COPY low 16 bits from HL

That source constraint was unnecessary and rejects valid inputs such as o16
virtual registers, causing instruction selection failures like:

  cannot select: %...:o16(s16) = G_SHL %...:o16, %...:gpr(s8)

Remove the unnecessary source constraint and constrain the fallback
destination to R16 instead of A16 after copying the low 16-bit result out of
HL.

This fixes backend crashes seen in real code such as invert_palette from
dino-run-ce, and adds a MIR regression test covering G_SHL on an o16 s16
input in eZ80 mode.

Co-Authored-By: Codex CLI <codex@openai.com>

Author: adriweb

llvm/lib/Target/Z80/GISel/Z80InstructionSelector.cpp

@@ -2962,8 +2962,6 @@ bool Z80InstructionSelector::selectShift(MachineInstr &I,
         .addImm(0)           // upper bits undefined (don't care)
         .addReg(SrcReg)      // source s16
           .addImm(Z80::sub_short);
-      if (!RBI.constrainGenericRegister(SrcReg, Z80::A16RegClass, MRI))
-        return false;
 
       // copy to physical UHL for ADD24aa operations
       BuildMI(MBB, InsertPt, DL, TII.get(TargetOpcode::COPY), Z80::UHL)
@@ -2979,7 +2977,7 @@ bool Z80InstructionSelector::selectShift(MachineInstr &I,
       MIB.buildCopy(DstReg, Register(Z80::HL));
 
       const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg);
-      if (!DstRC && !RBI.constrainGenericRegister(DstReg, Z80::A16RegClass, MRI)) {
+      if (!DstRC && !RBI.constrainGenericRegister(DstReg, Z80::R16RegClass, MRI)) {
         return false;
       }
       I.eraseFromParent();

llvm/test/CodeGen/Z80/shl-s16-o16-ez80.mir

@@ -0,0 +1,33 @@
+# RUN: llc -O0 -mtriple=ez80-none-elf -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+  define i16 @shl_s16_o16(i16 %x) { entry: ret i16 0 }
+...
+
+---
+name:            shl_s16_o16
+alignment:       1
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $de
+
+    ; CHECK-LABEL: name: shl_s16_o16
+    ; CHECK: [[EXT:%[0-9]+]]:a24 = SUBREG_TO_REG 0, [[SRC:%[0-9]+]], %subreg.sub_short
+    ; CHECK: $uhl = COPY [[EXT]]
+    ; CHECK: $uhl = ADD24aa $uhl
+    ; CHECK: $uhl = ADD24aa $uhl
+    ; CHECK: $uhl = ADD24aa $uhl
+    ; CHECK: $uhl = ADD24aa $uhl
+    ; CHECK: $uhl = ADD24aa $uhl
+    ; CHECK: [[DST:%[0-9]+]]:o16 = COPY $hl
+    ; CHECK: $hl = COPY [[DST]]
+    ; CHECK: RET24 implicit-def $spl, implicit $spl
+    %0:o16(s16) = COPY $de
+    %1:gpr(s8) = G_CONSTANT i8 5
+    %2:o16(s16) = G_SHL %0, %1(s8)
+    $hl = COPY %2(s16)
+    RET24 implicit-def $spl, implicit $spl
+...