feat: Apply numerous API fixes for LLVM v19

Signed-off-by: Sightem <sightem@national.shitposting.agency>

Author: Sightem

clang/tools/driver/cc1_main.cpp

@@ -288,15 +288,15 @@ int cc1_main(ArrayRef<const char *> Argv, const char *Argv0, void *MainAddr) {
     llvm::initializeCodeGen(Registry);
     llvm::initializeLoopStrengthReducePass(Registry);
     llvm::initializeLowerIntrinsicsPass(Registry);
-    llvm::initializeEntryExitInstrumenterPass(Registry);
+    llvm::initializePostInlineEntryExitInstrumenterPass(Registry);
     llvm::initializePostInlineEntryExitInstrumenterPass(Registry);
     llvm::initializeUnreachableBlockElimLegacyPassPass(Registry);
     llvm::initializeConstantHoistingLegacyPassPass(Registry);
     llvm::initializeScalarOpts(Registry);
     llvm::initializeVectorization(Registry);
     llvm::initializeScalarizeMaskedMemIntrinLegacyPassPass(Registry);
     llvm::initializeExpandReductionsPass(Registry);
-    llvm::initializeHardwareLoopsPass(Registry);
+    llvm::initializeHardwareLoopsLegacyPass(Registry);
     llvm::initializeTransformUtils(Registry);
   }
 

llvm/include/llvm/BinaryFormat/ELFRelocs/Z80.def

@@ -0,0 +1,19 @@
+
+#ifndef ELF_RELOC
+#error "ELF_RELOC must be defined"
+#endif
+
+ELF_RELOC(R_Z80_NONE,    0)
+ELF_RELOC(R_Z80_8,       1)
+ELF_RELOC(R_Z80_8_DIS,   2)
+ELF_RELOC(R_Z80_8_PCREL, 3)
+ELF_RELOC(R_Z80_16,      4)
+ELF_RELOC(R_Z80_24,      5)
+ELF_RELOC(R_Z80_32,      6)
+ELF_RELOC(R_Z80_BYTE0,   7)
+ELF_RELOC(R_Z80_BYTE1,   8)
+ELF_RELOC(R_Z80_BYTE2,   9)
+ELF_RELOC(R_Z80_BYTE3,   10)
+ELF_RELOC(R_Z80_WORD0,   11)
+ELF_RELOC(R_Z80_WORD1,   12)
+ELF_RELOC(R_Z80_16_BE,   13)

llvm/include/llvm/BinaryFormat/ELFRelocs/z80.def

@@ -0,0 +1 @@
+Z80.def

llvm/include/llvm/BinaryFormat/ELFRelocs/z80.def

@@ -848,8 +848,6 @@ class AsmPrinter : public MachineFunctionPass {
   static Align getGVAlignment(const GlobalObject *GV, const DataLayout &DL,
                               Align InAlign = Align(1));
 
-  virtual void emitGlobalAlias(Module &M, const GlobalAlias &GA);
-
 private:
   /// Private state for PrintSpecial()
   // Assign a unique ID to this machine instruction.

llvm/include/llvm/CodeGen/AsmPrinter.h

@@ -92,6 +92,54 @@ matchConstant<const IgnoreMatch>(Register Reg, const MachineRegisterInfo &MRI) {
   return std::optional<const IgnoreMatch>{ IgnoreMatch{} };
 }
 
+template <>
+inline std::optional<uint64_t>
+matchConstant<uint64_t>(Register Reg, const MachineRegisterInfo &MRI) {
+  if (auto Val = matchConstant<APInt>(Reg, MRI)) {
+    if (Val->getBitWidth() <= 64)
+      return Val->getZExtValue();
+  }
+  return std::nullopt;
+}
+
+template <>
+inline std::optional<int64_t>
+matchConstant<int64_t>(Register Reg, const MachineRegisterInfo &MRI) {
+  if (auto Val = matchConstant<APInt>(Reg, MRI)) {
+    if (Val->getBitWidth() <= 64)
+      return Val->getSExtValue();
+  }
+  return std::nullopt;
+}
+
+template <>
+inline std::optional<bool>
+matchConstant<bool>(Register Reg, const MachineRegisterInfo &MRI) {
+  if (auto Val = matchConstant<APInt>(Reg, MRI))
+    return Val->getBoolValue();
+  return std::nullopt;
+}
+
+template <>
+inline std::optional<unsigned>
+matchConstant<unsigned>(Register Reg, const MachineRegisterInfo &MRI) {
+  if (auto Val = matchConstant<APInt>(Reg, MRI)) {
+    if (Val->getBitWidth() <= 32)
+      return static_cast<unsigned>(Val->getZExtValue());
+  }
+  return std::nullopt;
+}
+
+template <>
+inline std::optional<unsigned char>
+matchConstant<unsigned char>(Register Reg, const MachineRegisterInfo &MRI) {
+  if (auto Val = matchConstant<APInt>(Reg, MRI)) {
+    if (Val->getBitWidth() <= 8)
+      return static_cast<unsigned char>(Val->getZExtValue());
+  }
+  return std::nullopt;
+}
+
 // template <typename ConstT>
 // inline std::optional<ConstT> matchConstant(Register Reg,
 //                                       const MachineRegisterInfo &MRI) {

llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h

@@ -6365,14 +6365,14 @@ bool CombinerHelper::matchBuildVectorIdentityFold(MachineInstr &MI,
     return MRI.getType(MatchInfo) == DstVecTy;
   }
 
-  std::optional<ValueAndVReg> ShiftAmount;
+  ValueAndVReg ShiftAmount;
   const auto LoPattern = m_GBitcast(m_Reg(Lo));
   const auto HiPattern = m_GLShr(m_GBitcast(m_Reg(Hi)), m_ICst(ShiftAmount));
   if (mi_match(
           MI, MRI,
           m_any_of(m_GBuildVectorTrunc(LoPattern, HiPattern),
                    m_GBuildVector(m_GTrunc(LoPattern), m_GTrunc(HiPattern))))) {
-    if (Lo == Hi && ShiftAmount->Value == DstEltTy.getSizeInBits()) {
+    if (Lo == Hi && ShiftAmount.Value == DstEltTy.getSizeInBits()) {
       MatchInfo = Lo;
       return MRI.getType(MatchInfo) == DstVecTy;
     }
@@ -6396,14 +6396,14 @@ bool CombinerHelper::matchTruncLshrBuildVectorFold(MachineInstr &MI,
                                                    Register &MatchInfo) {
   // Replace (G_TRUNC (G_LSHR (G_BITCAST (G_BUILD_VECTOR x, y)), K)) with
   //    y if K == size of vector element type
-  std::optional<ValueAndVReg> ShiftAmt;
+  ValueAndVReg ShiftAmt;
   if (!mi_match(MI.getOperand(1).getReg(), MRI,
                 m_GLShr(m_GBitcast(m_GBuildVector(m_Reg(), m_Reg(MatchInfo))),
                         m_ICst(ShiftAmt))))
     return false;
 
   LLT MatchTy = MRI.getType(MatchInfo);
-  return ShiftAmt->Value.getZExtValue() == MatchTy.getSizeInBits() &&
+  return ShiftAmt.Value.getZExtValue() == MatchTy.getSizeInBits() &&
          MatchTy == MRI.getType(MI.getOperand(0).getReg());
 }
 

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

@@ -536,7 +536,7 @@ Register llvm::getSrcRegIgnoringCopies(Register Reg,
 /// Returns -1 in the first element of the pair if the breakdown is not
 /// satisfiable.
 std::pair<int, int>
-getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
+llvm::getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
   unsigned Size = OrigTy.getSizeInBits();
   unsigned NarrowSize = NarrowTy.getSizeInBits();
   unsigned NumParts = Size / NarrowSize;

llvm/lib/CodeGen/GlobalISel/Utils.cpp

@@ -6,9 +6,9 @@ tablegen(LLVM EZ80GenAsmWriter.inc -gen-asm-writer -asmwriternum=1)
 tablegen(LLVM Z80GenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM Z80GenCallingConv.inc -gen-callingconv)
 tablegen(LLVM Z80GenPostLegalizeGICombiner.inc -gen-global-isel-combiner
-              -combiners="Z80PostLegalizerCombinerHelper")
+              -combiners="Z80PostLegalizerCombiner")
 tablegen(LLVM Z80GenPreLegalizeGICombiner.inc -gen-global-isel-combiner
-              -combiners="Z80PreLegalizerCombinerHelper")
+              -combiners="Z80PreLegalizerCombiner")
 tablegen(LLVM Z80GenGlobalISel.inc -gen-global-isel)
 tablegen(LLVM Z80GenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM Z80GenRegisterBank.inc -gen-register-bank)

llvm/lib/Target/Z80/CMakeLists.txt

@@ -24,6 +24,7 @@
 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/Target/TargetMachine.h"
 using namespace llvm;
 using namespace MIPatternMatch;
@@ -59,13 +60,13 @@ struct Z80OutgoingValueHandler : public CallLowering::OutgoingValueHandler {
   }
 
   void assignValueToReg(Register ValVReg, Register PhysReg,
-                        CCValAssign VA) override {
+                        const CCValAssign &VA) override {
     MIB.addReg(PhysReg, RegState::Implicit);
     MIRBuilder.buildCopy(PhysReg, ValVReg);
   }
 
   void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
-                            MachinePointerInfo &MPO, CCValAssign &VA) override {
+                            const MachinePointerInfo &MPO, const CCValAssign &VA) override {
     auto MMO = MIRBuilder.getMF().getMachineMemOperand(
         MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
         Align());
@@ -123,7 +124,7 @@ struct CallArgHandler : public Z80OutgoingValueHandler {
         StackPushes(MIRBuilder.getInsertPt()), RegCopies(StackPushes) {}
 
   void assignValueToReg(Register ValVReg, Register PhysReg,
-                        CCValAssign VA) override {
+                        const CCValAssign &VA) override {
     auto SaveInsertPt = std::prev(MIRBuilder.getInsertPt());
     --StackPushes;
     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), RegCopies);
@@ -140,7 +141,7 @@ struct CallArgHandler : public Z80OutgoingValueHandler {
   }
 
   void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
-                            MachinePointerInfo &MPO, CCValAssign &VA) override {
+                            const MachinePointerInfo &MPO, const CCValAssign &VA) override {
     LLT SlotTy = LLT::scalar(DL.getIndexSizeInBits(0));
     if (VA.getLocVT().getStoreSize() != SlotTy.getSizeInBytes() ||
         !mi_match(Addr, MRI,
@@ -167,7 +168,7 @@ struct CallArgHandler : public Z80OutgoingValueHandler {
   }
 
   bool finalize(CCState &State) override {
-    FrameSize = State.getNextStackOffset();
+    FrameSize = State.getStackSize();
     bool Success = Z80OutgoingValueHandler::finalize(State);
     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), RegCopies);
     return Success;
@@ -215,15 +216,15 @@ struct Z80IncomingValueHandler : public CallLowering::IncomingValueHandler {
   }
 
   void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
-                            MachinePointerInfo &MPO, CCValAssign &VA) override {
+                            const MachinePointerInfo &MPO, const CCValAssign &VA) override {
     auto MMO = MIRBuilder.getMF().getMachineMemOperand(
         MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, MemTy,
         Align());
     MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
   }
 
   void assignValueToReg(Register ValVReg, Register PhysReg,
-                        CCValAssign VA) override {
+                        const CCValAssign &VA) override {
     markPhysRegUsed(PhysReg);
     MIRBuilder.buildCopy(ValVReg, PhysReg);
   }
@@ -249,10 +250,10 @@ struct FormalArgHandler : public Z80IncomingValueHandler {
   bool finalize(CCState &State) override {
     MachineFunction &MF = MIRBuilder.getMF();
     auto &FuncInfo = *MF.getInfo<Z80MachineFunctionInfo>();
-    FuncInfo.setArgFrameSize(State.getNextStackOffset());
+    FuncInfo.setArgFrameSize(State.getStackSize());
     if (State.isVarArg()) {
       int FrameIdx = MF.getFrameInfo().CreateFixedObject(
-          1, State.getNextStackOffset(), true);
+          1, State.getStackSize(), true);
       FuncInfo.setVarArgsFrameIndex(FrameIdx);
     }
     return true;
@@ -346,7 +347,7 @@ bool Z80CallLowering::areCalleeOutgoingArgsTailCallable(
 
   // Make sure that they can fit on the caller's stack.
   const auto &FuncInfo = *MF.getInfo<Z80MachineFunctionInfo>();
-  if (OutInfo.getNextStackOffset() > FuncInfo.getArgFrameSize()) {
+  if (OutInfo.getStackSize() > FuncInfo.getArgFrameSize()) {
     LLVM_DEBUG(dbgs() << "... Cannot fit call operands on caller's stack.\n");
     return false;
   }
@@ -761,7 +762,7 @@ bool Z80CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
   if (!MBB.empty())
     MIRBuilder.setInstr(*MBB.begin());
 
-  OutgoingValueAssigner Assigner(CC_Z80);
+  IncomingValueAssigner Assigner(CC_Z80);
   FormalArgHandler Handler(MIRBuilder, MRI);
   if (!determineAndHandleAssignments(Handler, Assigner, SplitArgs, MIRBuilder,
                                      F.getCallingConv(), F.isVarArg()))
@@ -796,7 +797,7 @@ bool Z80CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
   Type *RetTy = nullptr;
   if (SRetReturnReg) {
     VRegs = SRetReturnReg;
-    RetTy = Type::getInt8PtrTy(Ctx);
+    RetTy = PointerType::getUnqual(Ctx);
   } else if (!VRegs.empty())
     RetTy = Val->getType();