[Z80] Handle byte-aligned extracts from wide eZ80 tuple registers.

Fix GlobalISel instruction selection for byte-aligned G_EXTRACT operations
from R32_24, R48_24, and R64_24 tuple registers in eZ80 mode.

At higher optimization levels, some code paths materialize 24-bit-mode wide
tuples and then extract an 8-bit value at offset 24. The selector handled
direct subregister extracts and a spill/reload fallback for smaller source
classes, but it had no fallback for wide tuple classes, which caused
instruction selection to abort on cases like:

    G_EXTRACT %src:r64_24(s64), 24

Teach selectExtract() to spill the tuple components of R32_24/R48_24/R64_24
to a temporary stack slot and reload the requested byte-aligned slice.

Add a MIR regression test covering extraction of an 8-bit value from an
R64_24 source at offset 24.

Co-Authored-By: Codex CLI <codex@openai.com>

Author: adriweb

llvm/lib/Target/Z80/GISel/Z80InstructionSelector.cpp

@@ -1952,8 +1952,56 @@ bool Z80InstructionSelector::selectExtract(MachineInstr &I,
     const TargetRegisterClass *WideSrcRC = SrcRC;
     unsigned Opc;
     MachineIRBuilder MIB(I);
+    auto BuildStore = [&](unsigned StoreOpc, Register Reg, int FI,
+                          unsigned ByteOffset,
+                          unsigned SubReg = Z80::NoSubRegister) {
+      auto Store = MIB.buildInstr(StoreOpc).addFrameIndex(FI).addImm(ByteOffset);
+      if (SubReg == Z80::NoSubRegister)
+        Store.addReg(Reg);
+      else
+        Store.addReg(Reg, 0, SubReg);
+      return constrainSelectedInstRegOperands(*Store, TII, TRI, RBI);
+    };
+    auto BuildLoad = [&](unsigned LoadOpc, Register Reg, int FI,
+                         unsigned ByteOffset) {
+      auto Load = MIB.buildInstr(LoadOpc, {Reg}, {})
+                      .addFrameIndex(FI)
+                      .addImm(ByteOffset);
+      return constrainSelectedInstRegOperands(*Load, TII, TRI, RBI);
+    };
     int FI = MF.getFrameInfo().CreateStackObject(
         TRI.getSpillSize(*SrcRC), TRI.getSpillAlign(*SrcRC), false);
+    if (STI.is24Bit() &&
+        (SrcRC == &Z80::R32_24RegClass || SrcRC == &Z80::R48_24RegClass ||
+         SrcRC == &Z80::R64_24RegClass)) {
+      if (!BuildStore(Z80::LD24or, SrcReg, FI, 0, Z80::sub_low24))
+        return false;
+      if (SrcRC == &Z80::R32_24RegClass) {
+        if (!BuildStore(Z80::LD8or, SrcReg, FI, 3, Z80::sub_high8))
+          return false;
+      } else {
+        if (!BuildStore(Z80::LD24or, SrcReg, FI, 3, Z80::sub_mid24))
+          return false;
+        if (SrcRC == &Z80::R64_24RegClass &&
+            !BuildStore(STI.has16BitEZ80Ops() ? Z80::LD16or : Z80::LD88or,
+                        SrcReg, FI, 6, Z80::sub_word3))
+          return false;
+      }
+
+      if (DstRC == &Z80::R8RegClass)
+        Opc = Z80::LD8ro;
+      else if (DstRC == &Z80::R16RegClass)
+        Opc = STI.has16BitEZ80Ops() ? Z80::LD16ro : Z80::LD88ro;
+      else if (DstRC == &Z80::R24RegClass)
+        Opc = Z80::LD24ro;
+      else
+        return false;
+
+      if (!BuildLoad(Opc, DstReg, FI, Offset / 8))
+        return false;
+      I.eraseFromParent();
+      return true;
+    }
     if (STI.is24Bit() && SrcRC == &Z80::R16RegClass) {
       WideSrcRC = &Z80::R24RegClass;
       if (SrcReg.isPhysical())
@@ -1973,7 +2021,8 @@ bool Z80InstructionSelector::selectExtract(MachineInstr &I,
       Opc = Z80::LD24or;
     else
       return false;
-    MIB.buildInstr(Opc).addFrameIndex(FI).addImm(0).addReg(WideSrcReg);
+    if (!BuildStore(Opc, WideSrcReg, FI, 0))
+      return false;
     if (STI.is24Bit() && DstRC == &Z80::R16RegClass) {
       WideDstRC = &Z80::R24RegClass;
       if (DstReg.isPhysical())
@@ -1990,7 +2039,8 @@ bool Z80InstructionSelector::selectExtract(MachineInstr &I,
       Opc = Z80::LD24ro;
     else
       return false;
-    MIB.buildInstr(Opc, {WideDstReg}, {}).addFrameIndex(FI).addImm(Offset / 8);
+    if (!BuildLoad(Opc, WideDstReg, FI, Offset / 8))
+      return false;
     if (WideDstReg != DstReg) {
       if (!select(*MIB.buildTrunc(DstReg, WideDstReg)) ||
           !RBI.constrainGenericRegister(WideDstReg, *WideDstRC, MRI))

llvm/test/CodeGen/Z80/extract-byte-from-r64-24.mir

@@ -0,0 +1,32 @@
+# RUN: llc -O0 -mtriple=ez80-none-elf -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+  define i8 @extract_mid_byte() { entry: ret i8 0 }
+...
+
+---
+name:            extract_mid_byte
+alignment:       1
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: extract_mid_byte
+    ; CHECK: LD24or
+    ; CHECK: LD24or
+    ; CHECK: LD{{16|88}}or
+    ; CHECK: LD8ro
+    %0:gpr(s8) = G_CONSTANT i8 1
+    %1:gpr(s8) = G_CONSTANT i8 0
+    %2:gpr(s24) = G_MERGE_VALUES %0(s8), %1(s8), %1(s8)
+    %3:gpr(s24) = G_CONSTANT i24 0
+    %4:gpr(s16) = G_EXTRACT %3(s24), 0
+    %5:gpr(s64) = G_IMPLICIT_DEF
+    %6:gpr(s64) = G_INSERT %5, %2(s24), 0
+    %7:gpr(s64) = G_INSERT %6, %3(s24), 24
+    %8:gpr(s64) = G_INSERT %7, %4(s16), 48
+    %9:gpr(s8) = G_EXTRACT %8(s64), 24
+    $a = COPY %9(s8)
+    RET24 implicit-def $spl, implicit $spl
+...