[Z80] update and add more codegen tests

Author: adriweb

llvm/test/CodeGen/Z80/cmp-zero-postra.mir

@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 # RUN: llc -mtriple=ez80 -run-pass=postrapseudos -o - %s | FileCheck %s
 
 # Check O16/O24 source handling for Cmp16a0/Cmp24a0 pseudo expansion.
@@ -54,3 +55,5 @@ body: |
     liveins: $uhl
     Cmp24a0 killed $uhl, implicit-def $f, implicit-def dead $uhl
 ...
+## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+# CHECK: {{.*}}

llvm/test/CodeGen/Z80/extract-byte-from-r64-24.ll

@@ -0,0 +1,57 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=ez80 < %s | FileCheck %s --check-prefix=EZ80
+
+define i8 @extract_mid_byte32(i32 %x) {
+; EZ80-LABEL: extract_mid_byte32:
+; EZ80:       ; %bb.0: ; %entry
+; EZ80-NEXT:    ld iy, 0
+; EZ80-NEXT:    add iy, sp
+; EZ80-NEXT:    ld bc, (iy + 3)
+; EZ80-NEXT:    ld l, 24
+; EZ80-NEXT:    ld a, (iy + 6)
+; EZ80-NEXT:    call __lshru
+; EZ80-NEXT:    ld a, c
+; EZ80-NEXT:    ret
+entry:
+  %shr = lshr i32 %x, 24
+  %res = trunc i32 %shr to i8
+  ret i8 %res
+}
+
+define i8 @extract_mid_byte48(i48 %x) {
+; EZ80-LABEL: extract_mid_byte48:
+; EZ80:       ; %bb.0: ; %entry
+; EZ80-NEXT:    ld iy, 0
+; EZ80-NEXT:    add iy, sp
+; EZ80-NEXT:    ld hl, (iy + 3)
+; EZ80-NEXT:    ld de, (iy + 6)
+; EZ80-NEXT:    ld c, 24
+; EZ80-NEXT:    call __i48shru
+; EZ80-NEXT:    ld a, l
+; EZ80-NEXT:    ret
+entry:
+  %shr = lshr i48 %x, 24
+  %res = trunc i48 %shr to i8
+  ret i8 %res
+}
+
+define i8 @extract_mid_byte64(i64 %x) {
+; EZ80-LABEL: extract_mid_byte64:
+; EZ80:       ; %bb.0: ; %entry
+; EZ80-NEXT:    ld iy, 0
+; EZ80-NEXT:    add iy, sp
+; EZ80-NEXT:    ld hl, (iy + 3)
+; EZ80-NEXT:    ld de, (iy + 6)
+; EZ80-NEXT:    ld bc, (iy + 9)
+; EZ80-NEXT:    ld iy, 24
+; EZ80-NEXT:    push iy
+; EZ80-NEXT:    ; kill: def $bc killed $bc killed $ubc
+; EZ80-NEXT:    call __llshru
+; EZ80-NEXT:    pop de
+; EZ80-NEXT:    ld a, l
+; EZ80-NEXT:    ret
+entry:
+  %shr = lshr i64 %x, 24
+  %res = trunc i64 %shr to i8
+  ret i8 %res
+}

llvm/test/CodeGen/Z80/shl-s16-o16-ez80-asm.mir

@@ -0,0 +1,47 @@
+# RUN: llc -mtriple=ez80-none-elf -start-after=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+# CHECK-LABEL: _shl_s16_o16:
+# CHECK:       ld l, e
+# CHECK-NEXT:  ld h, d
+# CHECK-NEXT:  add hl, hl
+# CHECK-NEXT:  add hl, hl
+# CHECK-NEXT:  add hl, hl
+# CHECK-NEXT:  add hl, hl
+# CHECK-NEXT:  add hl, hl
+# CHECK-NEXT:  ret
+
+--- |
+  define i16 @shl_s16_o16(i16 %x) {
+  entry:
+    ret i16 0
+  }
+
+...
+---
+name:            shl_s16_o16
+alignment:       1
+legalized:       true
+regBankSelected: true
+selected:        true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: o16, preferred-register: '' }
+  - { id: 2, class: o16, preferred-register: '' }
+  - { id: 3, class: a24, preferred-register: '' }
+body:             |
+  bb.0.entry:
+    liveins: $de
+
+    %0:o16 = COPY $de
+    %3:a24 = SUBREG_TO_REG 0, %0, %subreg.sub_short
+    $uhl = COPY %3
+    $uhl = ADD24aa $uhl, implicit-def $f
+    $uhl = ADD24aa $uhl, implicit-def $f
+    $uhl = ADD24aa $uhl, implicit-def $f
+    $uhl = ADD24aa $uhl, implicit-def $f
+    $uhl = ADD24aa $uhl, implicit-def $f
+    %2:o16 = COPY $hl
+    $hl = COPY %2
+    RET24 implicit-def $spl, implicit $spl, implicit $hl
+
+...