fix compil

adriweb · adriweb · commit ff036fab941b · 2025-02-27T14:23:12.000+01:00
diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td
@@ -1942,7 +1942,7 @@ def AnyZ80Interrupt : InheritableAttr, TargetSpecificAttr<TargetAnyZ80> {
   // MipsInterrupt's and AnyX86Interrupt's spellings must match.
   let Spellings = [GNU<"interrupt">];
   let Subjects = SubjectList<[Function]>;
-  let Args = [EnumArgument<"Interrupt", "InterruptType",
+  let Args = [EnumArgument<"Interrupt", "InterruptType", /*is_string=*/true,
                            ["", "nested", "nmi"],
                            ["Generic", "Nested", "NMI"],
                            1>];
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
@@ -195,6 +195,7 @@ class SemaSwift;
 class SemaSystemZ;
 class SemaWasm;
 class SemaX86;
+class SemaZ80;
 class StandardConversionSequence;
 class Stmt;
 class StringLiteral;
@@ -1261,6 +1262,11 @@ class Sema final : public SemaBase {
     return *X86Ptr;
   }
 
+  SemaZ80 &Z80() {
+    assert(Z80Ptr);
+    return *Z80Ptr;
+  }
+
   /// Source of additional semantic information.
   IntrusiveRefCntPtr<ExternalSemaSource> ExternalSource;
 
@@ -1316,6 +1322,7 @@ class Sema final : public SemaBase {
   std::unique_ptr<SemaSystemZ> SystemZPtr;
   std::unique_ptr<SemaWasm> WasmPtr;
   std::unique_ptr<SemaX86> X86Ptr;
+  std::unique_ptr<SemaZ80> Z80Ptr;
 
   ///@}
 
diff --git a/clang/include/clang/Sema/SemaZ80.h b/clang/include/clang/Sema/SemaZ80.h
@@ -26,7 +26,7 @@ class SemaZ80 : public SemaBase {
 public:
   SemaZ80(Sema &S);
 
-  void handleZ80InterruptAttr(Sema &S, Decl *D, const ParsedAttr &AL)
+  void handleZ80InterruptAttr(Decl *D, const ParsedAttr &AL);
 };
 } // namespace clang
 
diff --git a/clang/lib/Basic/Targets/Z80.cpp b/clang/lib/Basic/Targets/Z80.cpp
@@ -203,7 +203,7 @@ Z80TargetInfoBase::convertConstraint(const char *&Constraint) const {
 }
 
 ArrayRef<TargetInfo::AddlRegName> Z80TargetInfoBase::getGCCAddlRegNames() const {
-  return llvm::makeArrayRef(AddlRegNames);
+  return ArrayRef(AddlRegNames);
 }
 
 bool Z80TargetInfo::setCPU(const std::string &Name) {
@@ -240,12 +240,11 @@ void Z80TargetInfo::getTargetDefines(const LangOptions &Opts,
 }
 
 ArrayRef<Builtin::Info> Z80TargetInfo::getTargetBuiltins() const {
-  return llvm::makeArrayRef(BuiltinInfoZ80, Z80::LastZ80CommonBuiltin -
-                                                Builtin::FirstTSBuiltin + 1);
+  return {}; // ArrayRef(BuiltinInfoZ80, Z80::LastZ80CommonBuiltin - Builtin::FirstTSBuiltin + 1);
 }
 
 ArrayRef<const char *> Z80TargetInfo::getGCCRegNames() const {
-  return llvm::makeArrayRef(Z80GCCRegNames);
+  return ArrayRef(Z80GCCRegNames);
 }
 
 bool EZ80TargetInfo::setCPU(const std::string &Name) {
@@ -263,10 +262,10 @@ void EZ80TargetInfo::getTargetDefines(const LangOptions &Opts,
 }
 
 ArrayRef<Builtin::Info> EZ80TargetInfo::getTargetBuiltins() const {
-  return llvm::makeArrayRef(BuiltinInfoZ80,
+  return ArrayRef(BuiltinInfoZ80,
                             Z80::LastTSBuiltin - Builtin::FirstTSBuiltin);
 }
 
 ArrayRef<const char *> EZ80TargetInfo::getGCCRegNames() const {
-  return llvm::makeArrayRef(EZ80GCCRegNames);
+  return ArrayRef(EZ80GCCRegNames);
 }
diff --git a/clang/lib/CodeGen/ABIInfoImpl.cpp b/clang/lib/CodeGen/ABIInfoImpl.cpp
@@ -238,13 +238,14 @@ RValue CodeGen::emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr,
   return CGF.EmitLoadOfAnyValue(CGF.MakeAddrLValue(Addr, ValueTy), Slot);
 }
 
-Address CodeGen::emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr,
+RValue CodeGen::emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr,
                          QualType ValueTy, bool IsIndirect,
                          TypeInfoChars ValueInfo, CharUnits SlotSizeAndAlign,
-                         bool AllowHigherAlign, bool ForceRightAdjust) {
+                         bool AllowHigherAlign, AggValueSlot Slot,
+                         bool ForceRightAdjust) {
   return emitVoidPtrVAArg(CGF, VAListAddr, ValueTy, IsIndirect, ValueInfo,
                           SlotSizeAndAlign, SlotSizeAndAlign, AllowHigherAlign,
-                          ForceRightAdjust);
+                          Slot, ForceRightAdjust);
 }
 
 Address CodeGen::emitMergePHI(CodeGenFunction &CGF, Address Addr1,
diff --git a/clang/lib/CodeGen/ABIInfoImpl.h b/clang/lib/CodeGen/ABIInfoImpl.h
@@ -119,14 +119,14 @@ Address emitVoidPtrDirectVAArg(CodeGenFunction &CGF, Address VAListAddr,
 RValue emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr,
                          QualType ValueTy, bool IsIndirect,
                          TypeInfoChars ValueInfo, CharUnits SlotSize,
-                         CharUnits SlotAlign,
-                         bool AllowHigherAlign, bool ForceRightAdjust = false);
-
-Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr,
-                        QualType ValueTy, bool IsIndirect,
-                        TypeInfoChars ValueInfo, CharUnits SlotSizeAndAlign,
-                        bool AllowHigherAlign, AggValueSlot Slot,
-                        bool ForceRightAdjust = false);
+                         CharUnits SlotAlign, bool AllowHigherAlign,
+                         AggValueSlot Slot, bool ForceRightAdjust = false);
+
+RValue emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr,
+                         QualType ValueTy, bool IsIndirect,
+                         TypeInfoChars ValueInfo, CharUnits SlotSizeAndAlign,
+                         bool AllowHigherAlign, AggValueSlot Slot,
+                         bool ForceRightAdjust = false);
 
 Address emitMergePHI(CodeGenFunction &CGF, Address Addr1,
                      llvm::BasicBlock *Block1, Address Addr2,
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -22084,7 +22084,7 @@ Value *CodeGenFunction::EmitZ80BuiltinExpr(unsigned BuiltinID,
                                            const CallExpr *E) {
   switch (BuiltinID) {
   case Z80::BI__builtin_bitreverse24:
-    return emitUnaryBuiltin(*this, E, Intrinsic::bitreverse);
+    return emitBuiltinWithOneOverloadedType<1>(*this, E, Intrinsic::bitreverse);
   default:
     return nullptr;
   }
diff --git a/clang/lib/CodeGen/Targets/Z80.cpp b/clang/lib/CodeGen/Targets/Z80.cpp
@@ -32,8 +32,8 @@ class Z80ABIInfo : public DefaultABIInfo {
       removeExtend(Arg.info = classifyArgumentType(Arg.type));
   }
 
-  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
-                    QualType Ty) const override;
+  RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
+                   QualType Ty, AggValueSlot Slot) const override;
 };
 
 class Z80TargetCodeGenInfo : public TargetCodeGenInfo {
@@ -45,15 +45,18 @@ class Z80TargetCodeGenInfo : public TargetCodeGenInfo {
 };
 } // namespace
 
-Address Z80ABIInfo::EmitVAArg(CodeGenFunction &CGF,
-                              Address VAListAddr, QualType Ty) const {
-  Address Addr = emitVoidPtrVAArg(
+RValue Z80ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
+                             QualType Ty, AggValueSlot Slot) const {
+  return emitVoidPtrVAArg(
       CGF, VAListAddr, Ty, /*Indirect*/ false,
       getContext().getTypeInfoInChars(Ty),
-      CharUnits::fromQuantity(getDataLayout().getPointerSize()),
-      CharUnits::One(), /*AllowHigherAlign*/ false);
+      /*SlotSize*/ CharUnits::fromQuantity(getDataLayout().getPointerSize()),
+      /*SlotAlign*/ CharUnits::One(),
+      /*AllowHigherAlign*/ false,
+      Slot);
+  // TODO adriweb: comment by jacobly:
   // Remove SlotSize over-alignment, since stack is never aligned.
-  return Address(Addr.getPointer(), Addr.getType(), CharUnits::fromQuantity(1));
+  // return Address(Addr.getPointer(), CharUnits::fromQuantity(1));
 }
 
 void Z80TargetCodeGenInfo::setTargetAttributes(
diff --git a/clang/lib/Driver/ToolChains/Arch/Z80.cpp b/clang/lib/Driver/ToolChains/Arch/Z80.cpp
@@ -13,7 +13,6 @@
 #include "clang/Driver/Options.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/Option/ArgList.h"
-#include "llvm/Support/Host.h"
 
 using namespace clang::driver;
 using namespace clang::driver::tools;
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
@@ -68,6 +68,7 @@
 #include "clang/Sema/SemaSystemZ.h"
 #include "clang/Sema/SemaWasm.h"
 #include "clang/Sema/SemaX86.h"
+#include "clang/Sema/SemaZ80.h"
 #include "clang/Sema/TemplateDeduction.h"
 #include "clang/Sema/TemplateInstCallback.h"
 #include "clang/Sema/TypoCorrection.h"
@@ -247,6 +248,7 @@ Sema::Sema(Preprocessor &pp, ASTContext &ctxt, ASTConsumer &consumer,
       SystemZPtr(std::make_unique<SemaSystemZ>(*this)),
       WasmPtr(std::make_unique<SemaWasm>(*this)),
       X86Ptr(std::make_unique<SemaX86>(*this)),
+      Z80Ptr(std::make_unique<SemaZ80>(*this)),
       MSPointerToMemberRepresentationMethod(
           LangOpts.getMSPointerToMemberRepresentationMethod()),
       MSStructPragmaOn(false), VtorDispStack(LangOpts.getVtorDispMode()),
diff --git a/clang/lib/Sema/SemaZ80.cpp b/clang/lib/Sema/SemaZ80.cpp
@@ -24,7 +24,7 @@ namespace clang {
 
 SemaZ80::SemaZ80(Sema &S) : SemaBase(S) {}
 
-void SemaZ80::handleZ80InterruptAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
+void SemaZ80::handleZ80InterruptAttr(Decl *D, const ParsedAttr &AL) {
   if (!D->getDeclContext()->isFunctionOrMethod()) {
     Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)
         << "'interrupt'" << ExpectedFunction;
@@ -44,12 +44,12 @@ void SemaZ80::handleZ80InterruptAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
   }
 
   // The attribute takes an optional string argument.
-  if (!AL.checkAtMostNumArgs(S, 1))
+  if (!AL.checkAtMostNumArgs(SemaRef, 1))
     return;
 
   StringRef Str;
   SourceLocation ArgLoc;
-  if (AL.getNumArgs() && !S.checkStringLiteralArgumentAttr(AL, 0, Str, &ArgLoc))
+  if (AL.getNumArgs() && !SemaRef.checkStringLiteralArgumentAttr(AL, 0, Str, &ArgLoc))
     return;
 
   AnyZ80InterruptAttr::InterruptType Kind;
@@ -59,7 +59,7 @@ void SemaZ80::handleZ80InterruptAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
     Kind = AnyZ80InterruptAttr::InterruptType::Generic;
   }
 
-  D->addAttr(::new (S.Context) AnyZ80InterruptAttr(S.Context, AL, Kind));
+  D->addAttr(::new (SemaRef.Context) AnyZ80InterruptAttr(SemaRef.Context, AL, Kind));
 }
 
 } // namespace clang
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
@@ -249,6 +249,9 @@ MachineInstr *getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI,
 Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI,
                                  bool HasOneNonDBGUse = false);
 
+std::pair<int, int>
+getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy);
+
 /// Helper function to split a wide generic register into bitwise blocks with
 /// the given Type (which implies the number of blocks needed). The generic
 /// registers created are appended to Ops, starting at bit 0 of Reg.
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -598,7 +598,7 @@ static void buildCopyToRegs(MachineIRBuilder &B, ArrayRef<Register> DstRegs,
   }
 
   if (!SrcTy.isVector() && !PartTy.isVector()) {
-    if (SrcSize == PartSize * DstRegs.size()) {
+    if (SrcSize == PartSize.getFixedValue() * DstRegs.size()) {
       B.buildUnmerge(DstRegs, SrcReg);
       return;
     }
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -1133,13 +1133,6 @@ bool CombinerHelper::canMove(MachineInstr &MI, MachineBasicBlock &MBB,
   return true;
 }
 
-static Type *getTypeForLLT(LLT Ty, LLVMContext &C) {
-  if (Ty.isVector())
-    return FixedVectorType::get(IntegerType::get(C, Ty.getScalarSizeInBits()),
-                                Ty.getNumElements());
-  return IntegerType::get(C, Ty.getSizeInBits());
-}
-
 /// Return true if 'MI' is a load or a store that may be fold it's address
 /// operand into the load / store addressing mode.
 static bool canFoldInAddressingMode(GLoadStore *MI, const TargetLowering &TLI,
@@ -7092,8 +7085,8 @@ bool CombinerHelper::matchNarrowLoad(MachineInstr &MI,
   const auto *MMO = MatchInfo.MI->memoperands().front();
   LLT AddrTy = MRI.getType(MatchInfo.MI->getOperand(1).getReg());
   return !MMO->isVolatile() && !MMO->isAtomic() &&
-         MMO->getSizeInBits() >= DstSize &&
-         MatchInfo.Imm <= int64_t(MMO->getSizeInBits() - DstSize) &&
+         MMO->getSizeInBits().getValue() >= DstSize &&
+         MatchInfo.Imm <= int64_t(MMO->getSizeInBits().getValue() - DstSize) &&
          isLegalOrBeforeLegalizer({TargetOpcode::G_LOAD, {DstTy, AddrTy}});
 }
 
@@ -7264,9 +7257,9 @@ bool CombinerHelper::matchSimplifyICmpBool(MachineInstr &MI,
   MatchInfo.Imm = 0;
   ConstantInt *BoolCI[2] = {ConstantInt::getFalse(C), ConstantInt::getTrue(C)};
   for (ConstantInt *InCI : BoolCI)
-    if (Constant *ResC =
-            ConstantExpr::getCompare(Pred, InCI, BoolCI[CmpVal], true))
-      MatchInfo.Imm = MatchInfo.Imm << 1 | (ResC == BoolCI[true]);
+    if (const auto& ResC =
+            ICmpInst::compare(InCI->getValue(), BoolCI[CmpVal]->getValue(), Pred))
+      MatchInfo.Imm = MatchInfo.Imm << 1 | (ResC == BoolCI[true]->getValue());
     else
       return false;
   return true;
diff --git a/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp b/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
@@ -111,8 +111,6 @@ static bool isArtifact(const MachineInstr &MI) {
   case TargetOpcode::G_EXTRACT:
   case TargetOpcode::G_INSERT:
     return true;
-  case TargetOpcode::G_INSERT:
-    return AllowGInsertAsArtifact;
   }
 }
 using InstListTy = GISelWorkList<256>;
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -45,41 +45,6 @@ using namespace llvm;
 using namespace LegalizeActions;
 using namespace MIPatternMatch;
 
-/// Try to break down \p OrigTy into \p NarrowTy sized pieces.
-///
-/// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
-/// with any leftover piece as type \p LeftoverTy
-///
-/// Returns -1 in the first element of the pair if the breakdown is not
-/// satisfiable.
-static std::pair<int, int>
-getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
-  unsigned Size = OrigTy.getSizeInBits();
-  unsigned NarrowSize = NarrowTy.getSizeInBits();
-  unsigned NumParts = Size / NarrowSize;
-  unsigned LeftoverSize = Size - NumParts * NarrowSize;
-  assert(Size > NarrowSize);
-
-  if (LeftoverSize == 0)
-    return {NumParts, 0};
-
-  LLT CorrectLeftoverTy;
-  if (NarrowTy.isVector()) {
-    unsigned EltSize = OrigTy.getScalarSizeInBits();
-    if (LeftoverSize % EltSize != 0)
-      return {-1, -1};
-    CorrectLeftoverTy = LLT::scalarOrVector(
-        ElementCount::getFixed(LeftoverSize / EltSize), EltSize);
-  } else {
-    CorrectLeftoverTy = LLT::scalar(LeftoverSize);
-  }
-  assert((!LeftoverTy.isValid() || LeftoverTy == CorrectLeftoverTy) &&
-         "LeftoverTy already set to wrong value");
-  LeftoverTy = CorrectLeftoverTy;
-
-  return {NumParts, LeftoverSize / LeftoverTy.getSizeInBits()};
-}
-
 static Type *getFloatTypeForLLT(LLVMContext &Ctx, LLT Ty) {
 
   if (!Ty.isScalar())
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -528,6 +528,42 @@ Register llvm::getSrcRegIgnoringCopies(Register Reg,
   return DefSrcReg ? DefSrcReg->Reg : Register();
 }
 
+/// Try to break down \p OrigTy into \p NarrowTy sized pieces.
+///
+/// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
+/// with any leftover piece as type \p LeftoverTy
+///
+/// Returns -1 in the first element of the pair if the breakdown is not
+/// satisfiable.
+std::pair<int, int>
+getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
+  unsigned Size = OrigTy.getSizeInBits();
+  unsigned NarrowSize = NarrowTy.getSizeInBits();
+  unsigned NumParts = Size / NarrowSize;
+  unsigned LeftoverSize = Size - NumParts * NarrowSize;
+  assert(Size > NarrowSize);
+
+  if (LeftoverSize == 0)
+    return {NumParts, 0};
+
+  LLT CorrectLeftoverTy;
+  if (NarrowTy.isVector()) {
+    unsigned EltSize = OrigTy.getScalarSizeInBits();
+    if (LeftoverSize % EltSize != 0)
+      return {-1, -1};
+    CorrectLeftoverTy = LLT::scalarOrVector(
+        ElementCount::getFixed(LeftoverSize / EltSize), EltSize);
+  } else {
+    CorrectLeftoverTy = LLT::scalar(LeftoverSize);
+  }
+  assert((!LeftoverTy.isValid() || LeftoverTy == CorrectLeftoverTy) &&
+         "LeftoverTy already set to wrong value");
+  LeftoverTy = CorrectLeftoverTy;
+
+  return {NumParts, LeftoverSize / LeftoverTy.getSizeInBits()};
+}
+
+
 void llvm::extractParts(Register Reg, LLT Ty, int NumParts,
                         SmallVectorImpl<Register> &VRegs,
                         MachineIRBuilder &MIRBuilder,
diff --git a/llvm/lib/Target/Z80/Z80Combine.td b/llvm/lib/Target/Z80/Z80Combine.td
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp

Original file line number	Diff line number	Diff line change
`@@ -203,7 +203,7 @@ Z80TargetInfoBase::convertConstraint(const char *&Constraint) const {`
`203`	`203`	`}`
`204`	`204`
`205`	`205`	`ArrayRef<TargetInfo::AddlRegName> Z80TargetInfoBase::getGCCAddlRegNames() const {`
`206`		`- return llvm::makeArrayRef(AddlRegNames);`
	`206`	`+ return ArrayRef(AddlRegNames);`
`207`	`207`	`}`
`208`	`208`
`209`	`209`	`bool Z80TargetInfo::setCPU(const std::string &Name) {`
`@@ -240,12 +240,11 @@ void Z80TargetInfo::getTargetDefines(const LangOptions &Opts,`
`240`	`240`	`}`
`241`	`241`
`242`	`242`	`ArrayRef<Builtin::Info> Z80TargetInfo::getTargetBuiltins() const {`
`243`		`- return llvm::makeArrayRef(BuiltinInfoZ80, Z80::LastZ80CommonBuiltin -`
`244`		`- Builtin::FirstTSBuiltin + 1);`
	`243`	`+ return {}; // ArrayRef(BuiltinInfoZ80, Z80::LastZ80CommonBuiltin - Builtin::FirstTSBuiltin + 1);`
`245`	`244`	`}`
`246`	`245`
`247`	`246`	`ArrayRef<const char *> Z80TargetInfo::getGCCRegNames() const {`
`248`		`- return llvm::makeArrayRef(Z80GCCRegNames);`
	`247`	`+ return ArrayRef(Z80GCCRegNames);`
`249`	`248`	`}`
`250`	`249`
`251`	`250`	`bool EZ80TargetInfo::setCPU(const std::string &Name) {`
`@@ -263,10 +262,10 @@ void EZ80TargetInfo::getTargetDefines(const LangOptions &Opts,`
`263`	`262`	`}`
`264`	`263`
`265`	`264`	`ArrayRef<Builtin::Info> EZ80TargetInfo::getTargetBuiltins() const {`
`266`		`- return llvm::makeArrayRef(BuiltinInfoZ80,`
	`265`	`+ return ArrayRef(BuiltinInfoZ80,`
`267`	`266`	`Z80::LastTSBuiltin - Builtin::FirstTSBuiltin);`
`268`	`267`	`}`
`269`	`268`
`270`	`269`	`ArrayRef<const char *> EZ80TargetInfo::getGCCRegNames() const {`
`271`		`- return llvm::makeArrayRef(EZ80GCCRegNames);`
	`270`	`+ return ArrayRef(EZ80GCCRegNames);`
`272`	`271`	`}`
Original file line number	Diff line number	Diff line change
`@@ -22084,7 +22084,7 @@ Value *CodeGenFunction::EmitZ80BuiltinExpr(unsigned BuiltinID,`
`22084`	`22084`	`const CallExpr *E) {`
`22085`	`22085`	`switch (BuiltinID) {`
`22086`	`22086`	`case Z80::BI__builtin_bitreverse24:`
`22087`		`- return emitUnaryBuiltin(*this, E, Intrinsic::bitreverse);`
	`22087`	`+ return emitBuiltinWithOneOverloadedType<1>(*this, E, Intrinsic::bitreverse);`
`22088`	`22088`	`default:`
`22089`	`22089`	`return nullptr;`
`22090`	`22090`	`}`