Quickstart

Requirements

• PROLEAD is installed.

Getting Help

To verify that PROLEAD was successfully installed and to view a list of available command-line options, run the following command in your terminal:

PROLEAD -h

This will display a help message with usage instructions and a summary of all supported parameters. A list of all available command line parameters is also given here.

Hardware Evaluation

To evaluate a masked hardware design using PROLEAD, you will need the following components:

• Masked hardware design – A gate-level netlist written in Verilog.
• Cell library – A JSON file defining the characteristics of the logic gates used.
• Configuration file – A JSON file specifying the evaluation parameters.

The following sections explain how to obtain and prepare each of these required files.

Note: To get familiar with the required files, you can run the default example using the simple command: PROLEAD
This will evaluate the netlist design.v using the cell library located at libs/nang45.json and the configuration file config.json.

Preparing a Masked Hardware Design

Do you have a masked hardware design you'd like to analyze with PROLEAD? Great! To get started, simply synthesize your design into a gate-level Verilog netlist. We encourage you to use the synthesizer and standard-cell library of your choice. So far, PROLEAD has been successfully applied to netlists synthesized using the following configurations:

• We used the comercially available Synopsys DC for ASIC synthesis along with the Nangate 45 nm standard-cell library.
• We used the open-source tool Yosys along with a custom standard-cell library to get an ASIC netlist.
• We used the Vivado Design Suite from AMD with the UltraScale library to receive an FPGA netlist.

Note: Designing masked hardware even at the behavioral level can be challenging. If you're new to hardware masking or looking to simplify the development of masked circuits, consider using AGEMA. With AGEMA, you only need to provide your unmasked hardware design—the tool will automatically generate a masked version for you.

Preparing a Cell Library

PROLEAD requires a custom cell library that defines the behavior of the cells used in your netlist. Accurate simulation is only possible if the library correctly specifies all cell functionalities. Fortunately, if you used one of the synthesis procedures listed above, we've already done the work for you and prepared compatible cell libraries. Depending on your synthesis setup, we recommend using one of the following libraries:

• The nang45 library you can find here.
• The custom library you can find here.
• The xilinx_fpga library you can find here.

Note: Is a specific gate required in your netlist missing from our provided libraries? Or is your preferred standard-cell library currently unsupported? We're here to help! You can request support for additional libraries by starting a discussion, or, if you prefer, write your own cell library.

Preparing a Configuration File for Hardware

Running the Hardware Evaluation

Software Evaluation

To evaluate a masked software using PROLEAD, you will need the following components:

• Masked Software – Files written C or ARM assembly or an externally compiled binary.
• Linker Script – A .ld file.
• Configuration file – A JSON file specifying the evaluation parameters.

The following sections explain how to obtain and prepare each of these required files.

Implement a Custom Masked Software

You can implement your masked software using any number of source and header files written in either C or ARM assembly.

Currently, we support ARM instructions from the following instruction sets:

• ARMv6-M
• ARMv7-M
• ARMv7E-M (including the DSP extension)

Note: Floating-point and vector instructions are not supported at this time.

If you're unsure which instructions fall under these categories, we recommend referring to page 6 of the Cortex-M for Beginners guide.

Configuring PROLEAD for your Binary

Running the Software Evaluation

Interpreting the Results