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[CHIA-3769] - Update GMP to 6.3.0 and include new patch files #270

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Merged
hoffmang9 merged 4 commits into from
Feb 20, 2026
Merged

[CHIA-3769] - Update GMP to 6.3.0 and include new patch files #270

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166f8a2
add patch files for GMP6.3.0 and adjust build steps
emlowe Oct 1, 2025
fbec9a4
Update compat.patch for compatibility changes
altendky Oct 2, 2025
65a521b
a different take on the patching
altendky Oct 2, 2025
0ceeeb9
Merge pull request #273 from Chia-Network/altendky-patch-2
emlowe Nov 5, 2025
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11 changes: 5 additions & 6 deletions pyproject.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -19,12 +19,11 @@ yum -y install epel-release \
&& echo "epel-release installed" \
&& yum -y install boost-devel lzip \
&& echo "boost-devel and lzip installed" \
&& curl -L https://ftp.gnu.org/gnu/gmp/gmp-6.2.1.tar.lz | tar x --lzip \
&& cp src/lib/gmp-patch-6.2.1/longlong.h gmp-6.2.1/ \
&& cp src/lib/gmp-patch-6.2.1/compat.c gmp-6.2.1/ \
&& cp src/lib/gmp-patch-6.2.1/mpz/inp_raw.c gmp-6.2.1/mpz \
&& cd gmp-6.2.1 && ./configure --enable-fat --enable-cxx \
&& make && make install && cd .. && rm -rf gmp-6.2.1 \
&& curl -L https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.lz | tar x --lzip \
&& cd gmp-6.3.0 \
&& patch < ../src/lib/gmp-6.3.0.diff \
&& ./configure --enable-fat --enable-cxx \
&& make && make install && cd .. && rm -rf gmp-6.3.0 \
&& cmake --version \
&& uname -a \
"""
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220 changes: 220 additions & 0 deletions src/lib/gmp-6.2.1.diff
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@@ -0,0 +1,220 @@
diff --git a/compat.c b/compat.c
index b4b44ce..3f563dd 100644
--- a/compat.c
+++ b/compat.c
@@ -31,6 +31,12 @@ see https://www.gnu.org/licenses/. */
#include <stdio.h>
#include "gmp-impl.h"

+/* RUNTIMECPUID */
+int bCheckedBMI = 0;
+int bBMI1 = 0;
+int bBMI2 = 0;
+int bCheckedLZCNT = 0;
+int bLZCNT = 0;

/* mpn_divexact_by3 was a function in gmp 3.0.1, but as of gmp 3.1 it's a
macro calling mpn_divexact_by3c. */
diff --git a/longlong.h b/longlong.h
index edbaf56..c0a7468 100644
--- a/longlong.h
+++ b/longlong.h
@@ -1040,6 +1040,86 @@ extern UWtype __MPN(udiv_qrnnd) (UWtype *, UWtype, UWtype, UWtype);
#endif /* 80x86 */

#if defined (__amd64__) && W_TYPE_SIZE == 64
+
+#ifndef RUNTIMECPUID
+#define RUNTIMECPUID
+
+extern int bCheckedBMI;
+extern int bBMI1;
+extern int bBMI2;
+
+inline void hasBMI()
+{
+ if(bCheckedBMI)
+ return;
+
+ bCheckedBMI = 1;
+ int info[4] = {0};
+#if defined(_MSC_VER)
+ __cpuid(info, 0x7);
+#elif defined(__GNUC__) || defined(__clang__)
+#if defined(ARCH_X86) && defined(__PIC__)
+ __asm__ __volatile__ (
+ "xchg{l} {%%}ebx, %k1;"
+ "cpuid;"
+ "xchg{l} {%%}ebx, %k1;"
+ : "=a"(info[0]), "=&r"(info[1]), "=c"(info[2]), "=d"(info[3]) : "a"(0x7), "c"(0)
+ );
+#else
+ __asm__ __volatile__ (
+ "cpuid" : "=a"(info[0]), "=b"(info[1]), "=c"(info[2]), "=d"(info[3]) : "a"(0x7), "c"(0)
+ );
+#endif
+#endif
+ bBMI1 = ((info[1] & (1 << 3)) != 0);
+ bBMI2 = ((info[1] & (1 << 8)) != 0);
+}
+
+inline int hasBMI1()
+{
+ hasBMI();
+ return bBMI1;
+}
+
+inline int hasBMI2()
+{
+ hasBMI();
+ return bBMI2;
+}
+
+extern int bCheckedLZCNT;
+extern int bLZCNT;
+
+inline int hasLZCNT()
+{
+ if(bCheckedLZCNT)
+ return bLZCNT;
+
+ bCheckedLZCNT = 1;
+ int info[4] = {0};
+ #if defined(_MSC_VER)
+ __cpuid(info, 0x80000001);
+ #elif defined(__GNUC__) || defined(__clang__)
+ #if defined(ARCH_X86) && defined(__PIC__)
+ __asm__ __volatile__ (
+ "xchg{l} {%%}ebx, %k1;"
+ "cpuid;"
+ "xchg{l} {%%}ebx, %k1;"
+ : "=a"(info[0]), "=&r"(info[1]), "=c"(info[2]), "=d"(info[3]) : "a"(0x80000001), "c"(0)
+ );
+ #else
+ __asm__ __volatile__ (
+ "cpuid" : "=a"(info[0]), "=b"(info[1]), "=c"(info[2]), "=d"(info[3]) : "a"(0x80000001), "c"(0)
+ );
+ #endif
+ #endif
+
+ bLZCNT = ((info[2] & (1 << 5)) != 0);
+ return bLZCNT;
+}
+
+#endif // RUNTIMECPUID
+
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addq %5,%q1\n\tadcq %3,%q0" \
: "=r" (sh), "=&r" (sl) \
@@ -1050,61 +1130,52 @@ extern UWtype __MPN(udiv_qrnnd) (UWtype *, UWtype, UWtype, UWtype);
: "=r" (sh), "=&r" (sl) \
: "0" ((UDItype)(ah)), "rme" ((UDItype)(bh)), \
"1" ((UDItype)(al)), "rme" ((UDItype)(bl)))
-#if X86_ASM_MULX \
- && (HAVE_HOST_CPU_haswell || HAVE_HOST_CPU_broadwell \
- || HAVE_HOST_CPU_skylake || HAVE_HOST_CPU_bd4 || HAVE_HOST_CPU_zen)
#define umul_ppmm(w1, w0, u, v) \
- __asm__ ("mulx\t%3, %q0, %q1" \
+ if(hasBMI2()) { \
+ __asm__ ("mulx\t%3, %q0, %q1" \
: "=r" (w0), "=r" (w1) \
- : "%d" ((UDItype)(u)), "rm" ((UDItype)(v)))
-#else
-#define umul_ppmm(w1, w0, u, v) \
- __asm__ ("mulq\t%3" \
+ : "%d" ((UDItype)(u)), "rm" ((UDItype)(v))); \
+ } else { \
+ __asm__ ("mulq\t%3" \
: "=a" (w0), "=d" (w1) \
- : "%0" ((UDItype)(u)), "rm" ((UDItype)(v)))
-#endif
+ : "%0" ((UDItype)(u)), "rm" ((UDItype)(v))); \
+ }
#define udiv_qrnnd(q, r, n1, n0, dx) /* d renamed to dx avoiding "=d" */\
__asm__ ("divq %4" /* stringification in K&R C */ \
: "=a" (q), "=d" (r) \
: "0" ((UDItype)(n0)), "1" ((UDItype)(n1)), "rm" ((UDItype)(dx)))

-#if HAVE_HOST_CPU_haswell || HAVE_HOST_CPU_broadwell || HAVE_HOST_CPU_skylake \
- || HAVE_HOST_CPU_k10 || HAVE_HOST_CPU_bd1 || HAVE_HOST_CPU_bd2 \
- || HAVE_HOST_CPU_bd3 || HAVE_HOST_CPU_bd4 || HAVE_HOST_CPU_zen \
- || HAVE_HOST_CPU_bobcat || HAVE_HOST_CPU_jaguar
#define count_leading_zeros(count, x) \
- do { \
- /* This is lzcnt, spelled for older assemblers. Destination and */ \
- /* source must be a 64-bit registers, hence cast and %q. */ \
- __asm__ ("rep;bsr\t%1, %q0" : "=r" (count) : "rm" ((UDItype)(x))); \
- } while (0)
+ if(hasLZCNT()) { \
+ do { \
+ /* This is lzcnt, spelled for older assemblers. Destination and */ \
+ /* source must be a 64-bit registers, hence cast and %q. */ \
+ __asm__ ("rep;bsr\t%1, %q0" : "=r" (count) : "rm" ((UDItype)(x))); \
+ } while (0); \
+ } else { \
+ do { \
+ UDItype __cbtmp; \
+ ASSERT ((x) != 0); \
+ __asm__ ("bsr\t%1,%0" : "=r" (__cbtmp) : "rm" ((UDItype)(x))); \
+ (count) = __cbtmp ^ 63; \
+ } while (0); \
+ }
#define COUNT_LEADING_ZEROS_0 64
-#else
-#define count_leading_zeros(count, x) \
- do { \
- UDItype __cbtmp; \
- ASSERT ((x) != 0); \
- __asm__ ("bsr\t%1,%0" : "=r" (__cbtmp) : "rm" ((UDItype)(x))); \
- (count) = __cbtmp ^ 63; \
- } while (0)
-#endif

-#if HAVE_HOST_CPU_bd2 || HAVE_HOST_CPU_bd3 || HAVE_HOST_CPU_bd4 \
- || HAVE_HOST_CPU_zen || HAVE_HOST_CPU_jaguar
#define count_trailing_zeros(count, x) \
- do { \
- /* This is tzcnt, spelled for older assemblers. Destination and */ \
- /* source must be a 64-bit registers, hence cast and %q. */ \
- __asm__ ("rep;bsf\t%1, %q0" : "=r" (count) : "rm" ((UDItype)(x))); \
- } while (0)
+ if(hasBMI1()) { \
+ do { \
+ /* This is tzcnt, spelled for older assemblers. Destination and */ \
+ /* source must be a 64-bit registers, hence cast and %q. */ \
+ __asm__ ("rep;bsf\t%1, %q0" : "=r" (count) : "rm" ((UDItype)(x))); \
+ } while (0); \
+ } else { \
+ do { \
+ ASSERT ((x) != 0); \
+ __asm__ ("bsf\t%1, %q0" : "=r" (count) : "rm" ((UDItype)(x))); \
+ } while (0); \
+ }
#define COUNT_TRAILING_ZEROS_0 64
-#else
-#define count_trailing_zeros(count, x) \
- do { \
- ASSERT ((x) != 0); \
- __asm__ ("bsf\t%1, %q0" : "=r" (count) : "rm" ((UDItype)(x))); \
- } while (0)
-#endif
#endif /* __amd64__ */

#if defined (__i860__) && W_TYPE_SIZE == 32
diff --git a/mpz/inp_raw.c b/mpz/inp_raw.c
index 378c42b..f88fea9 100644
--- a/mpz/inp_raw.c
+++ b/mpz/inp_raw.c
@@ -88,8 +88,11 @@ mpz_inp_raw (mpz_ptr x, FILE *fp)

abs_csize = ABS (csize);

+ if (UNLIKELY (abs_csize > ~(mp_bitcnt_t) 0 / 8))
+ return 0; /* Bit size overflows */
+
/* round up to a multiple of limbs */
- abs_xsize = BITS_TO_LIMBS (abs_csize*8);
+ abs_xsize = BITS_TO_LIMBS ((mp_bitcnt_t) abs_csize * 8);

if (abs_xsize != 0)
{
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