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riscv64.yml
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Test RISC-V Backend Test RISC-V Backend #17: Scheduled
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Test RISC-V Backend Test RISC-V Backend #16: Scheduled
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Test RISC-V Backend Test RISC-V Backend #15: Scheduled
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Guard NSString.UTF8String against nil in ExecuTorchModule.mm Test RISC-V Backend #14: Commit 8fbfed9 pushed by qti-horodnic
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Test RISC-V Backend Test RISC-V Backend #13: Scheduled
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Arm backend: Enable CPPCHECK linting Test RISC-V Backend #12: Commit b4a9e72 pushed by chenweng-quic
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Add citing instructions for ExecuTorch (#19589) Test RISC-V Backend #11: Commit 64684c7 pushed by chenweng-quic
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Zephyr: Move CI testing to a script (#19542) Test RISC-V Backend #10: Commit 1feb56c pushed by qti-horodnic
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Revert PyTorch 2.12 pin bump (#19698) Test RISC-V Backend #9: Commit 3b5d18d pushed by qti-horodnic
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Test RISC-V Backend Test RISC-V Backend #8: Scheduled
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Fix race condition in XNNPACK weights cache during concurrent init() Test RISC-V Backend #7: Commit a4bd823 pushed by qti-horodnic
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Add MLX backend support for Gemma 4 31B (#19524) Test RISC-V Backend #6: Commit f8cfc73 pushed by qti-horodnic
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Test RISC-V Backend Test RISC-V Backend #5: Scheduled
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Guard weight_dequant.args[1] access in _quantize_fused_conv_bias pass Test RISC-V Backend #4: Commit d62addb pushed by qti-horodnic
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Test RISC-V Backend Test RISC-V Backend #3: Scheduled
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Test RISC-V Backend Test RISC-V Backend #2: Scheduled
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Prevent _safe_softmax decomposition in traceand rewire replaceSafeSof… Test RISC-V Backend #1: Commit 824cbff pushed by qti-horodnic
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