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Luo Jiequic-rjangir
Luo Jie
authored and
quic-rjangir
committed
qualcommbe: ipq54xx: Enable RDP487 Ethernet function
RDP487 is connected with QCA8386 switch via PPE port 3 and connected with QCA8111 PHY via PPE port 2. Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
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‎target/linux/qualcommbe/patches-6.12/0637-arm64-dts-ipq5424-rdp487-Add-Ethernet-related-DTS-no.patch‎

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From 36f9fc7a5f355f17777f2ea3cb0ce6f7c1e106b0 Mon Sep 17 00:00:00 2001
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From: Luo Jie <jie.luo@oss.qualcomm.com>
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Date: Tue, 2 Sep 2025 17:17:33 +0800
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Subject: [PATCH] arm64: dts: ipq5424-rdp487: Add Ethernet related DTS nodes
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RDP487 is connected with QCA8386 switch via PPE port 3 and connected with
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QCA8111 PHY via PPE port 2.
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Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
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---
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arch/arm64/boot/dts/qcom/ipq5424-rdp487.dts | 331 +++++++++++++++++++-
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1 file changed, 330 insertions(+), 1 deletion(-)
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diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp487.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp487.dts
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index d76c53d22b50..60a29bf95c52 100644
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--- a/arch/arm64/boot/dts/qcom/ipq5424-rdp487.dts
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+++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp487.dts
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@@ -8,6 +8,9 @@
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/dts-v1/;
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#include "ipq5424.dtsi"
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+#include <dt-bindings/clock/qcom,qca8k-nsscc.h>
23+
+#include <dt-bindings/net/qcom,qca808x.h>
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+#include <dt-bindings/reset/qcom,qca8k-nsscc.h>
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/ {
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model = "Qualcomm Technologies, Inc. IPQ5424 RDP487";
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@@ -17,6 +20,18 @@
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serial0 = &uart1;
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};
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+ qca8k_uniphy1_rx312p5m: qca8k-uniphy1-rx312p5m {
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+ compatible = "fixed-clock";
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+ clock-frequency = <312500000>;
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+ #clock-cells = <0>;
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+ };
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+
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+ qca8k_uniphy1_tx312p5m: qca8k-uniphy1-tx312p5m {
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+ compatible = "fixed-clock";
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+ clock-frequency = <312500000>;
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+ #clock-cells = <0>;
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+ };
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+
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vreg_misc_3p3: regulator-usb-3p3 {
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compatible = "regulator-fixed";
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regulator-min-microvolt = <3300000>;
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@@ -45,6 +60,300 @@
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};
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};
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+&mdio {
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+ clock-frequency = <6250000>;
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+ status = "okay";
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+
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+ ethernet-phy-package@1 {
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+ compatible = "qcom,qca8084-package";
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+ reg = <1>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ clocks = <&qca8k_nsscc NSS_CC_APB_BRIDGE_CLK>,
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+ <&qca8k_nsscc NSS_CC_AHB_CLK>,
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+ <&qca8k_nsscc NSS_CC_SEC_CTRL_AHB_CLK>,
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+ <&qca8k_nsscc NSS_CC_TLMM_CLK>,
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+ <&qca8k_nsscc NSS_CC_TLMM_AHB_CLK>,
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+ <&qca8k_nsscc NSS_CC_CNOC_AHB_CLK>,
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+ <&qca8k_nsscc NSS_CC_MDIO_AHB_CLK>,
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+ <&qca8k_nsscc NSS_CC_MDIO_MASTER_AHB_CLK>,
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+ <&qca8k_nsscc NSS_CC_SWITCH_CORE_CLK>;
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+ clock-names = "apb_bridge",
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+ "ahb",
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+ "sec_ctrl_ahb",
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+ "tlmm",
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+ "tlmm_ahb",
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+ "cnoc_ahb",
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+ "mdio_ahb",
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+ "mdio_master_ahb",
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+ "switch_core";
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+ resets = <&qca8k_nsscc NSS_CC_GEPHY_FULL_ARES>;
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+ qcom,package-mode = <QCA808X_PCS1_SGMII_MAC_PCS0_SGMII_MAC>;
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+ qcom,phy-addr-fixup = <1 2 3 4 5 6 7>;
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+
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+ dsa_phy0: ethernet-phy@1 {
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+ compatible = "ethernet-phy-id004d.d180";
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+ reg = <1>;
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+ clocks = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_CLK>;
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+ resets = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_ARES>;
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+ };
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+
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+ dsa_phy1: ethernet-phy@2 {
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+ compatible = "ethernet-phy-id004d.d180";
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+ reg = <2>;
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+ clocks = <&qca8k_nsscc NSS_CC_GEPHY1_SYS_CLK>;
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+ resets = <&qca8k_nsscc NSS_CC_GEPHY1_SYS_ARES>;
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+ };
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+
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+ dsa_phy2: ethernet-phy@3 {
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+ compatible = "ethernet-phy-id004d.d180";
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+ reg = <3>;
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+ clocks = <&qca8k_nsscc NSS_CC_GEPHY2_SYS_CLK>;
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+ resets = <&qca8k_nsscc NSS_CC_GEPHY2_SYS_ARES>;
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+ };
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+
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+ dsa_phy3: ethernet-phy@4 {
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+ compatible = "ethernet-phy-id004d.d180";
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+ reg = <4>;
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+ clocks = <&qca8k_nsscc NSS_CC_GEPHY3_SYS_CLK>;
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+ resets = <&qca8k_nsscc NSS_CC_GEPHY3_SYS_ARES>;
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+ };
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+ };
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+
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+ pcsphy1: pcsphy@6 {
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+ compatible = "qcom,qca8k_pcs";
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+ reg = <6>;
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+ #clock-cells = <0x1>;
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+
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+ clocks = <&qca8k_nsscc NSS_CC_SRDS1_SYS_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC0_RX_SRDS1_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC0_TX_SRDS1_CLK>;
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+ clock-names = "sys",
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+ "rx",
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+ "tx";
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+ resets = <&qca8k_nsscc NSS_CC_SRDS1_SYS_ARES>,
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+ <&qca8k_nsscc NSS_CC_MAC0_RX_SRDS1_ARES>,
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+ <&qca8k_nsscc NSS_CC_MAC0_TX_SRDS1_ARES>;
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+ reset-names = "sys",
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+ "rx",
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+ "tx";
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+ clock-output-names = "qca8k_uniphy_rx",
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+ "qca8k_uniphy_tx";
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+ };
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+
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+ switch@10 {
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+ compatible = "qca,qca8386";
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+ reg = <0x10>;
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+ clocks = <&qca8k_uniphy1_tx312p5m>;
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+ clock-names = "uniphy1_tx_312p5m_clk";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ qca8k_cpu_port: port@0 {
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+ reg = <0>;
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+ phy-mode = "2500base-x";
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+ pcsphy-handle = <&pcsphy1>;
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+ ethernet = <&ppe_port3>;
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+
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+ clocks = <&qca8k_nsscc NSS_CC_MAC0_RX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC0_TX_CLK>;
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+ clock-names = "port_rx_clk", "port_tx_clk";
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+ fixed-link {
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+ speed = <2500>;
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+ full-duplex;
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+ pause;
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+ };
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+
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ label = "lan1";
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+ phy-mode = "sgmii";
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+ phy-handle = <&dsa_phy0>;
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+
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+ clocks = <&qca8k_nsscc NSS_CC_MAC1_RX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC1_TX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC1_RX_CLK_SRC>,
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+ <&qca8k_nsscc NSS_CC_MAC1_TX_CLK_SRC>,
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+ <&qca8k_nsscc NSS_CC_MAC1_GEPHY0_RX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC1_GEPHY0_TX_CLK>;
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+ clock-names = "port_rx_clk", "port_tx_clk",
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+ "port_rx_src_clk", "port_tx_src_clk",
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+ "ephy_rx_clk", "ephy_tx_clk";
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+
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+ resets = <&qca8k_nsscc NSS_CC_MAC1_GEPHY0_RX_ARES>,
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+ <&qca8k_nsscc NSS_CC_MAC1_GEPHY0_TX_ARES>;
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+ reset-names = "ephy_rx_reset", "ephy_tx_reset";
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+
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ label = "lan2";
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+ phy-mode = "sgmii";
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+ phy-handle = <&dsa_phy1>;
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+
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+ clocks = <&qca8k_nsscc NSS_CC_MAC2_RX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC2_TX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC2_RX_CLK_SRC>,
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+ <&qca8k_nsscc NSS_CC_MAC2_TX_CLK_SRC>,
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+ <&qca8k_nsscc NSS_CC_MAC2_GEPHY1_RX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC2_GEPHY1_TX_CLK>;
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+ clock-names = "port_rx_clk", "port_tx_clk",
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+ "port_rx_src_clk", "port_tx_src_clk",
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+ "ephy_rx_clk", "ephy_tx_clk";
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+
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+ resets = <&qca8k_nsscc NSS_CC_MAC2_GEPHY1_RX_ARES>,
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+ <&qca8k_nsscc NSS_CC_MAC2_GEPHY1_TX_ARES>;
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+ reset-names = "ephy_rx_reset", "ephy_tx_reset";
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+ };
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+
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+ port@3 {
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+ reg = <3>;
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+ label = "lan3";
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+ phy-mode = "sgmii";
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+ phy-handle = <&dsa_phy2>;
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+
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+ clocks = <&qca8k_nsscc NSS_CC_MAC3_RX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC3_TX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC3_RX_CLK_SRC>,
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+ <&qca8k_nsscc NSS_CC_MAC3_TX_CLK_SRC>,
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+ <&qca8k_nsscc NSS_CC_MAC3_GEPHY2_RX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC3_GEPHY2_TX_CLK>;
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+ clock-names = "port_rx_clk", "port_tx_clk",
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+ "port_rx_src_clk", "port_tx_src_clk",
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+ "ephy_rx_clk", "ephy_tx_clk";
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+
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+ resets = <&qca8k_nsscc NSS_CC_MAC3_GEPHY2_RX_ARES>,
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+ <&qca8k_nsscc NSS_CC_MAC3_GEPHY2_TX_ARES>;
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+ reset-names = "ephy_rx_reset", "ephy_tx_reset";
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+ };
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+
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+ port@4 {
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+ reg = <4>;
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+ label = "lan4";
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+ phy-mode = "sgmii";
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+ phy-handle = <&dsa_phy3>;
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+
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+ clocks = <&qca8k_nsscc NSS_CC_MAC4_RX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC4_TX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC4_RX_CLK_SRC>,
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+ <&qca8k_nsscc NSS_CC_MAC4_TX_CLK_SRC>,
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+ <&qca8k_nsscc NSS_CC_MAC4_GEPHY3_RX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC4_GEPHY3_TX_CLK>;
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+ clock-names = "port_rx_clk", "port_tx_clk",
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+ "port_rx_src_clk", "port_tx_src_clk",
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+ "ephy_rx_clk", "ephy_tx_clk";
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+
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+ resets = <&qca8k_nsscc NSS_CC_MAC4_GEPHY3_RX_ARES>,
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+ <&qca8k_nsscc NSS_CC_MAC4_GEPHY3_TX_ARES>;
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+ reset-names = "ephy_rx_reset", "ephy_tx_reset";
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+ };
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+ };
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+ };
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+
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+ qca8k_nsscc: qca8k-nsscc@18 {
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+ compatible = "qcom,qca8084-nsscc";
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+ reg = <0x18>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ reset-gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
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+ clocks = <&cmn_pll IPQ5424_ETH2_50MHZ_CLK>,
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+ <0>,
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+ <0>,
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+ <&pcsphy1 0>,
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+ <&pcsphy1 1>,
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+ <&qca8k_uniphy1_rx312p5m>,
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+ <&qca8k_uniphy1_tx312p5m>;
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+ };
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+
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+ phy1: ethernet-phy@c {
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+ compatible ="ethernet-phy-ieee802.3-c45";
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+ reg = <0xc>;
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+ reset-gpios = <&tlmm 28 GPIO_ACTIVE_LOW>;
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+ reset-assert-us = <100000>;
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+ reset-deassert-us = <100000>;
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+ };
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+};
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+
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+&pcs1 {
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+ status = "okay";
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+};
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+
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+&pcs1_mii0 {
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+ clocks = <&nsscc NSS_CC_UNIPHY_PORT2_RX_CLK>,
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+ <&nsscc NSS_CC_UNIPHY_PORT2_TX_CLK>;
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+ clock-names = "rx",
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+ "tx";
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+ status = "okay";
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+};
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+
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+&pcs2 {
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+ status = "okay";
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+};
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+
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+&pcs2_mii0 {
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+ clocks = <&nsscc NSS_CC_UNIPHY_PORT3_RX_CLK>,
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+ <&nsscc NSS_CC_UNIPHY_PORT3_TX_CLK>;
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+ clock-names = "rx",
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+ "tx";
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+ status = "okay";
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+};
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+
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+&qcom_ppe {
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+ ethernet-ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@2 {
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+ reg = <2>;
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+ phy-mode = "usxgmii";
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+ managed = "in-band-status";
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+ label = "wan";
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+ phy-handle = <&phy1>;
305+
+ pcs-handle = <&pcs1_mii0>;
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+ clocks = <&nsscc NSS_CC_PORT2_MAC_CLK>,
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+ <&nsscc NSS_CC_PORT2_RX_CLK>,
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+ <&nsscc NSS_CC_PORT2_TX_CLK>;
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+ clock-names = "mac",
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+ "rx",
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+ "tx";
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+ resets = <&nsscc NSS_CC_PORT2_MAC_CLK_ARES>,
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+ <&nsscc NSS_CC_PORT2_RX_CLK_ARES>,
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+ <&nsscc NSS_CC_PORT2_TX_CLK_ARES>;
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+ reset-names = "mac",
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+ "rx",
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+ "tx";
318+
+ };
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+
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+ ppe_port3: port@3 {
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+ reg = <3>;
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+ phy-mode = "2500base-x";
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+ pcs-handle = <&pcs2_mii0>;
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+ clocks = <&nsscc NSS_CC_PORT3_MAC_CLK>,
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+ <&nsscc NSS_CC_PORT3_RX_CLK>,
326+
+ <&nsscc NSS_CC_PORT3_TX_CLK>;
327+
+ clock-names = "mac",
328+
+ "rx",
329+
+ "tx";
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+ resets = <&nsscc NSS_CC_PORT3_MAC_CLK_ARES>,
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+ <&nsscc NSS_CC_PORT3_RX_CLK_ARES>,
332+
+ <&nsscc NSS_CC_PORT3_TX_CLK_ARES>;
333+
+ reset-names = "mac",
334+
+ "rx",
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+ "tx";
336+
+ fixed-link {
337+
+ speed = <2500>;
338+
+ full-duplex;
339+
+ pause;
340+
+ };
341+
+ };
342+
+ };
343+
+};
344+
+
345+
&dwc_0 {
346+
dr_mode = "host";
347+
};
348+
@@ -140,6 +449,26 @@
349+
status = "okay";
350+
};
351+
352+
+/*
353+
+ * The bootstrap pins for the board select the XO clock frequency that
354+
+ * supports 48 MHZ, 96 MHZ or 192 MHZ. This setting automatically
355+
+ * enables the right dividers, to ensure the reference clock output
356+
+ * from WiFi to the CMN PLL is 48 MHZ.
357+
+ */
358+
+&ref_48mhz_clk {
359+
+ clock-div = <1>;
360+
+ clock-mult = <1>;
361+
+};
362+
+
363+
+/*
364+
+ * The frequency of xo_board is fixed to 24 MHZ, which is routed
365+
+ * from WiFi output clock 48 MHZ divided by 2.
366+
+ */
367+
&xo_board {
368+
- clock-frequency = <24000000>;
369+
+ clock-div = <2>;
370+
+ clock-mult = <1>;
371+
+};
372+
+
373+
+&xo_clk {
374+
+ clock-frequency = <48000000>;
375+
};
376+
--
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2.34.1
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