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ipq54xx : Fix DMA engine and MTD nand driver for spi nand probe
Here we are fixing the spi nand device probing for ipq54xx target with below fixes : 1. BAM_DESC_CNT_TRSHLD - Avoiding write to this unavailable register in BAM-Lite mode Enabling it to write only in BAM-NDP mode. 2. Enabling SPI nand support for ipq54xx with bam offset and compatiblity 3. Update qpic_nand and qpic_bam data in ipq54xx DTS files 4. Added a new field 'bam_offset' in the NAND properties structure and use it while preparing the command descriptor Signed-off-by: Vijay Balaji <quic_vijbal@quicinc.com>
1 parent f873418 commit cf99529

4 files changed

Lines changed: 443 additions & 0 deletions

‎target/linux/qualcommbe/patches-6.12/0638-dmaengine-qcom-bam_dma-Avoid-writing-unavailable-reg.patch‎

Lines changed: 83 additions & 0 deletions
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From 9b1f53dc7fc3d07e4632e5504d3309e7830d412c Mon Sep 17 00:00:00 2001
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From: Md Sadre Alam <mdalam@qti.qualcomm.com>
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Date: Thu, 4 Sep 2025 18:00:23 +0530
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Subject: dmaengine: qcom: bam_dma: Avoid writing unavailable
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register
6+
7+
Avoid writing unavailable register in BAM-Lite mode.
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BAM_DESC_CNT_TRSHLD register is unavailable in BAM-Lite
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mode. Its only available in BAM-NDP mode. So only write
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this register for clients who is using BAM-NDP.
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Signed-off-by: Md Sadre Alam <mdalam@qti.qualcomm.com>
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---
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drivers/dma/qcom/bam_dma.c | 21 +++++++++++++++------
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1 file changed, 15 insertions(+), 6 deletions(-)
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diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
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index 2cf060174795..86b19c287130 100644
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--- a/drivers/dma/qcom/bam_dma.c
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+++ b/drivers/dma/qcom/bam_dma.c
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@@ -59,6 +59,9 @@ struct bam_desc_hw {
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#define DESC_FLAG_NWD BIT(12)
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#define DESC_FLAG_CMD BIT(11)
24+
25+
+#define BAM_NDP_REVISION_START 0x20
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+#define BAM_NDP_REVISION_END 0x27
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+
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struct bam_async_desc {
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struct virt_dma_desc vd;
30+
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@@ -398,6 +401,7 @@ struct bam_device {
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/* dma start transaction tasklet */
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struct tasklet_struct task;
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+ u32 bam_revision;
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};
37+
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/**
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@@ -441,8 +445,10 @@ static void bam_reset(struct bam_device *bdev)
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writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
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/* set descriptor threshold, start with 4 bytes */
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- writel_relaxed(DEFAULT_CNT_THRSHLD,
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- bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
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+ if (in_range(bdev->bam_revision, BAM_NDP_REVISION_START,
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+ BAM_NDP_REVISION_END))
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+ writel_relaxed(DEFAULT_CNT_THRSHLD,
48+
+ bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
49+
50+
/* Enable default set of h/w workarounds, ie all except BAM_FULL_PIPE */
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writel_relaxed(BAM_CNFG_BITS_DEFAULT, bam_addr(bdev, 0, BAM_CNFG_BITS));
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@@ -1000,9 +1006,10 @@ static void bam_apply_new_config(struct bam_chan *bchan,
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maxburst = bchan->slave.src_maxburst;
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else
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maxburst = bchan->slave.dst_maxburst;
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-
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- writel_relaxed(maxburst,
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- bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
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+ if (in_range(bdev->bam_revision, BAM_NDP_REVISION_START,
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+ BAM_NDP_REVISION_END))
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+ writel_relaxed(maxburst,
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+ bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
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}
64+
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bchan->reconfigure = 0;
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@@ -1192,11 +1199,13 @@ static int bam_init(struct bam_device *bdev)
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u32 val;
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/* read revision and configuration information */
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+ val = readl_relaxed(bam_addr(bdev, 0, BAM_REVISION));
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if (!bdev->num_ees) {
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- val = readl_relaxed(bam_addr(bdev, 0, BAM_REVISION));
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bdev->num_ees = (val >> NUM_EES_SHIFT) & NUM_EES_MASK;
74+
}
75+
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+ bdev->bam_revision = val & REVISION_MASK;
77+
+
78+
/* check that configured EE is within range */
79+
if (bdev->ee >= bdev->num_ees)
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return -EINVAL;
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--
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2.34.1
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‎target/linux/qualcommbe/patches-6.12/0639-spi-spi-qpic-snand-Add-support-for-ipq5424-spi-nand.patch‎

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From c77141c38de8980f0cedad1cba1eb454ff7d9639 Mon Sep 17 00:00:00 2001
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From: Md Sadre Alam <mdalam@qti.qualcomm.com>
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Date: Thu, 4 Sep 2025 17:49:18 +0530
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Subject: spi: spi-qpic-snand: Add support for ipq5424 spi nand
5+
6+
Signed-off-by: Md Sadre Alam <mdalam@qti.qualcomm.com>
7+
---
8+
drivers/spi/spi-qpic-snand.c | 10 ++++++++++
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1 file changed, 10 insertions(+)
10+
11+
diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c
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index 2812ffc421d2..0f6f1ca3792a 100644
13+
--- a/drivers/spi/spi-qpic-snand.c
14+
+++ b/drivers/spi/spi-qpic-snand.c
15+
@@ -1649,11 +1649,21 @@ static const struct qcom_nandc_props ipq9574_snandc_props = {
16+
.supports_bam = true,
17+
};
18+
19+
+static const struct qcom_nandc_props ipq5424_snandc_props = {
20+
+ .dev_cmd_reg_start = 0x7000,
21+
+ .bam_offset = 0x30000,
22+
+ .supports_bam = true,
23+
+};
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+
25+
static const struct of_device_id qcom_snandc_of_match[] = {
26+
{
27+
.compatible = "qcom,ipq9574-snand",
28+
.data = &ipq9574_snandc_props,
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},
30+
+ {
31+
+ .compatible = "qcom,ipq5424-snand",
32+
+ .data = &ipq5424_snandc_props,
33+
+ },
34+
{}
35+
};
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MODULE_DEVICE_TABLE(of, qcom_snandc_of_match);
37+
--
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2.34.1
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‎target/linux/qualcommbe/patches-6.12/0640-arm64-ipq5424-enable-spi-nand-for-ipq5424-target.patch‎

Lines changed: 197 additions & 0 deletions
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From 49e93b9f13ecb267744adb75b0aad93ca5584820 Mon Sep 17 00:00:00 2001
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From: Md Sadre Alam <mdalam@qti.qualcomm.com>
3+
Date: Thu, 4 Sep 2025 17:44:50 +0530
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Subject: arm64: ipq5424: enable spi nand for ipq5424 target
5+
6+
Signed-off-by: Md Sadre Alam <mdalam@qti.qualcomm.com>
7+
---
8+
arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 72 ++++++++++++---------
9+
arch/arm64/boot/dts/qcom/ipq5424.dtsi | 27 ++++++++
10+
2 files changed, 70 insertions(+), 29 deletions(-)
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12+
diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
13+
index 738618551203..398638c52066 100644
14+
--- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
15+
+++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
16+
@@ -457,26 +457,26 @@
17+
};
18+
19+
&tlmm {
20+
- sdc_default_state: sdc-default-state {
21+
- clk-pins {
22+
+ qpic_snand_default_state: qpic-snand-default-state {
23+
+ qspi_clock {
24+
pins = "gpio5";
25+
- function = "sdc_clk";
26+
+ function = "qspi_clk";
27+
drive-strength = <8>;
28+
- bias-disable;
29+
+ bias-pull-down;
30+
};
31+
32+
- cmd-pins {
33+
+ qspi_cs {
34+
pins = "gpio4";
35+
- function = "sdc_cmd";
36+
+ function = "qspi_cs";
37+
drive-strength = <8>;
38+
bias-pull-up;
39+
};
40+
41+
- data-pins {
42+
+ qspi_data {
43+
pins = "gpio0", "gpio1", "gpio2", "gpio3";
44+
- function = "sdc_data";
45+
+ function = "qspi_data";
46+
drive-strength = <8>;
47+
- bias-pull-up;
48+
+ bias-pull-down;
49+
};
50+
};
51+
52+
@@ -271,6 +264,27 @@ &usb3 {
53+
status = "okay";
54+
};
55+
56+
+&qpic_bam {
57+
+ status = "okay";
58+
+};
59+
+
60+
+&qpic_nand {
61+
+ pinctrl-0 = <&qpic_snand_default_state>;
62+
+ pinctrl-names = "default";
63+
+
64+
+ status = "okay";
65+
+
66+
+ flash@0 {
67+
+ compatible = "spi-nand";
68+
+ reg = <0>;
69+
+ #address-cells = <1>;
70+
+ #size-cells = <1>;
71+
+ nand-ecc-engine = <&qpic_nand>;
72+
+ nand-ecc-strength = <8>;
73+
+ nand-ecc-step-size = <512>;
74+
+ };
75+
+};
76+
+
77+
/*
78+
* The bootstrap pins for the board select the XO clock frequency that
79+
* supports 48 MHZ, 96 MHZ or 192 MHZ. This setting automatically
80+
diff --git a/include/linux/dma/qcom_bam_dma.h b/include/linux/dma/qcom_bam_dma.h
81+
--- a/include/linux/dma/qcom_bam_dma.h
82+
+++ b/include/linux/dma/qcom_bam_dma.h
83+
@@ -67,5 +67,6 @@ bam_prep_ce(struct bam_cmd_element *bam_
84+
enum bam_command_type cmd, u32 data)
85+
{
86+
bam_prep_ce_le32(bam_ce, addr, cmd, cpu_to_le32(data));
87+
+ bam_ce->mask = 0x0;
88+
}
89+
#endif
90+
diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp487.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp487.dts
91+
--- a/arch/arm64/boot/dts/qcom/ipq5424-rdp487.dts
92+
+++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp487.dts
93+
@@ -403,26 +403,26 @@
94+
};
95+
96+
&tlmm {
97+
- sdc_default_state: sdc-default-state {
98+
- clk-pins {
99+
+ qpic_snand_default_state: qpic-snand-default-state {
100+
+ qspi_clock {
101+
pins = "gpio5";
102+
- function = "sdc_clk";
103+
+ function = "qspi_clk";
104+
drive-strength = <8>;
105+
- bias-disable;
106+
+ bias-pull-down;
107+
};
108+
109+
- cmd-pins {
110+
+ qspi_cs {
111+
pins = "gpio4";
112+
- function = "sdc_cmd";
113+
+ function = "qspi_cs";
114+
drive-strength = <8>;
115+
bias-pull-up;
116+
};
117+
118+
- data-pins {
119+
+ qspi_data {
120+
pins = "gpio0", "gpio1", "gpio2", "gpio3";
121+
- function = "sdc_data";
122+
+ function = "qspi_data";
123+
drive-strength = <8>;
124+
- bias-pull-up;
125+
+ bias-pull-down;
126+
};
127+
};
128+
129+
@@ -449,6 +449,27 @@
130+
status = "okay";
131+
};
132+
133+
+&qpic_bam {
134+
+ status = "okay";
135+
+};
136+
+
137+
+&qpic_nand {
138+
+ pinctrl-0 = <&qpic_snand_default_state>;
139+
+ pinctrl-names = "default";
140+
+
141+
+ status = "okay";
142+
+
143+
+ flash@0 {
144+
+ compatible = "spi-nand";
145+
+ reg = <0>;
146+
+ #address-cells = <1>;
147+
+ #size-cells = <1>;
148+
+ nand-ecc-engine = <&qpic_nand>;
149+
+ nand-ecc-strength = <8>;
150+
+ nand-ecc-step-size = <512>;
151+
+ };
152+
+};
153+
+
154+
/*
155+
* The bootstrap pins for the board select the XO clock frequency that
156+
* supports 48 MHZ, 96 MHZ or 192 MHZ. This setting automatically
157+
diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
158+
index bbb539dbdf5c..4b9f1d53fc0f 100644
159+
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
160+
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
161+
@@ -492,6 +492,33 @@ tcsr: syscon@1937000 {
162+
reg = <0 0x01937000 0 0x2a000>;
163+
};
164+
165+
+ qpic_bam: dma-controller@7984000 {
166+
+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
167+
+ reg = <0x0 0x07984000 0x0 0x1c000>;
168+
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
169+
+ clocks = <&gcc GCC_QPIC_AHB_CLK>;
170+
+ clock-names = "bam_clk";
171+
+ #dma-cells = <1>;
172+
+ qcom,ee = <0>;
173+
+ status = "disabled";
174+
+ };
175+
+
176+
+ qpic_nand: spi@79b0000 {
177+
+ compatible = "qcom,ipq5424-snand", "qcom,ipq5424-nand";
178+
+ reg = <0x0 0x079b0000 0x0 0x10000>;
179+
+ #address-cells = <1>;
180+
+ #size-cells = <0>;
181+
+ clocks = <&gcc GCC_QPIC_CLK>,
182+
+ <&gcc GCC_QPIC_AHB_CLK>,
183+
+ <&gcc GCC_QPIC_IO_MACRO_CLK>;
184+
+ clock-names = "core", "aon", "iom";
185+
+ dmas = <&qpic_bam 0>,
186+
+ <&qpic_bam 1>,
187+
+ <&qpic_bam 2>;
188+
+ dma-names = "tx", "rx", "cmd";
189+
+ status = "disabled";
190+
+ };
191+
+
192+
qupv3: geniqup@1ac0000 {
193+
compatible = "qcom,geni-se-qup";
194+
reg = <0 0x01ac0000 0 0x2000>;
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--
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2.34.1
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