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Luo Jiequic-rjangir
Luo Jie
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quic-rjangir
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qualcommbe: ipq54xx: Add initial support for RDP466 Ethernet function
IPQ54XX RDP466 is connected with two 10G QCA8111 PHYs and QCA8386 switch for the Ethernet function. Add the related drivers to enable these Ethernet hardware blocks. Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Signed-off-by: Ram Chandra Jangir <rjangir@qti.qualcomm.com>
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‎target/linux/qualcommbe/patches-6.12/0601-dt-bindings-clock-qcom-Add-CMN-PLL-support-for-IPQ54.patch‎

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From e596588715d53777cc3383a938247675295acc63 Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
3+
Date: Tue, 10 Jun 2025 18:35:18 +0800
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Subject: [PATCH 601/636] dt-bindings: clock: qcom: Add CMN PLL support for
5+
IPQ5424 SoC
6+
7+
The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference
8+
input clock. The output clocks are the same as IPQ9574 SoC, except
9+
for the clock rate of output clocks to PPE and NSS.
10+
11+
Also, add the new header file to export the CMN PLL output clock
12+
specifiers for IPQ5424 SoC.
13+
14+
Acked-by: Rob Herring (Arm) <robh@kernel.org>
15+
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
16+
---
17+
.../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 +
18+
.../dt-bindings/clock/qcom,ipq5424-cmn-pll.h | 22 +++++++++++++++++++
19+
2 files changed, 23 insertions(+)
20+
create mode 100644 include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h
21+
22+
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
23+
index f869b3739be8..cb6e09f4247f 100644
24+
--- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
25+
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
26+
@@ -24,6 +24,7 @@ description:
27+
properties:
28+
compatible:
29+
enum:
30+
+ - qcom,ipq5424-cmn-pll
31+
- qcom,ipq9574-cmn-pll
32+
33+
reg:
34+
diff --git a/include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h
35+
new file mode 100644
36+
index 000000000000..f643c2668c04
37+
--- /dev/null
38+
+++ b/include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h
39+
@@ -0,0 +1,22 @@
40+
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
41+
+/*
42+
+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
43+
+ */
44+
+
45+
+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5424_CMN_PLL_H
46+
+#define _DT_BINDINGS_CLK_QCOM_IPQ5424_CMN_PLL_H
47+
+
48+
+/* CMN PLL core clock. */
49+
+#define IPQ5424_CMN_PLL_CLK 0
50+
+
51+
+/* The output clocks from CMN PLL of IPQ5424. */
52+
+#define IPQ5424_XO_24MHZ_CLK 1
53+
+#define IPQ5424_SLEEP_32KHZ_CLK 2
54+
+#define IPQ5424_PCS_31P25MHZ_CLK 3
55+
+#define IPQ5424_NSS_300MHZ_CLK 4
56+
+#define IPQ5424_PPE_375MHZ_CLK 5
57+
+#define IPQ5424_ETH0_50MHZ_CLK 6
58+
+#define IPQ5424_ETH1_50MHZ_CLK 7
59+
+#define IPQ5424_ETH2_50MHZ_CLK 8
60+
+#define IPQ5424_ETH_25MHZ_CLK 9
61+
+#endif
62+
--
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2.34.1
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‎target/linux/qualcommbe/patches-6.12/0602-clk-qcom-cmnpll-Add-IPQ5424-SoC-support.patch‎

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From 253934e62a29e2b5147cdac86f6442a0d8f5460f Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
3+
Date: Tue, 10 Jun 2025 18:35:19 +0800
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Subject: [PATCH 602/636] clk: qcom: cmnpll: Add IPQ5424 SoC support
5+
6+
The CMN PLL in IPQ5424 SoC supplies the fixed clock to NSS at 300 MHZ
7+
and to PPE at 375 MHZ. Other output clocks from CMN PLL on this SoC,
8+
and their rates are same as IPQ9574.
9+
10+
Acked-by: Stephen Boyd <sboyd@kernel.org>
11+
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
12+
---
13+
drivers/clk/qcom/ipq-cmn-pll.c | 35 +++++++++++++++++++++++++++++-----
14+
1 file changed, 30 insertions(+), 5 deletions(-)
15+
16+
diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c
17+
index 432d4c4b7aa6..b34d6faf67b8 100644
18+
--- a/drivers/clk/qcom/ipq-cmn-pll.c
19+
+++ b/drivers/clk/qcom/ipq-cmn-pll.c
20+
@@ -1,6 +1,6 @@
21+
// SPDX-License-Identifier: GPL-2.0-only
22+
/*
23+
- * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
24+
+ * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
25+
*/
26+
27+
/*
28+
@@ -16,6 +16,10 @@
29+
* are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS
30+
* with 31.25 MHZ.
31+
*
32+
+ * On the IPQ5424 SoC, there is an output clock from CMN PLL to PPE at 375 MHZ,
33+
+ * and an output clock to NSS (network subsystem) at 300 MHZ. The other output
34+
+ * clocks from CMN PLL on IPQ5424 are the same as IPQ9574.
35+
+ *
36+
* +---------+
37+
* | GCC |
38+
* +--+---+--+
39+
@@ -46,6 +50,7 @@
40+
#include <linux/regmap.h>
41+
42+
#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
43+
+#include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h>
44+
45+
#define CMN_PLL_REFCLK_SRC_SELECTION 0x28
46+
#define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8)
47+
@@ -115,6 +120,20 @@ static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = {
48+
CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),
49+
CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL),
50+
CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
51+
+ { /* Sentinel */ }
52+
+};
53+
+
54+
+static const struct cmn_pll_fixed_output_clk ipq5424_output_clks[] = {
55+
+ CLK_PLL_OUTPUT(IPQ5424_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
56+
+ CLK_PLL_OUTPUT(IPQ5424_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
57+
+ CLK_PLL_OUTPUT(IPQ5424_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL),
58+
+ CLK_PLL_OUTPUT(IPQ5424_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL),
59+
+ CLK_PLL_OUTPUT(IPQ5424_PPE_375MHZ_CLK, "ppe-375mhz", 375000000UL),
60+
+ CLK_PLL_OUTPUT(IPQ5424_ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL),
61+
+ CLK_PLL_OUTPUT(IPQ5424_ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),
62+
+ CLK_PLL_OUTPUT(IPQ5424_ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL),
63+
+ CLK_PLL_OUTPUT(IPQ5424_ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
64+
+ { /* Sentinel */ }
65+
};
66+
67+
/*
68+
@@ -297,7 +316,7 @@ static struct clk_hw *ipq_cmn_pll_clk_hw_register(struct platform_device *pdev)
69+
70+
static int ipq_cmn_pll_register_clks(struct platform_device *pdev)
71+
{
72+
- const struct cmn_pll_fixed_output_clk *fixed_clk;
73+
+ const struct cmn_pll_fixed_output_clk *p, *fixed_clk;
74+
struct clk_hw_onecell_data *hw_data;
75+
struct device *dev = &pdev->dev;
76+
struct clk_hw *cmn_pll_hw;
77+
@@ -305,8 +324,13 @@ static int ipq_cmn_pll_register_clks(struct platform_device *pdev)
78+
struct clk_hw *hw;
79+
int ret, i;
80+
81+
- fixed_clk = ipq9574_output_clks;
82+
- num_clks = ARRAY_SIZE(ipq9574_output_clks);
83+
+ fixed_clk = device_get_match_data(dev);
84+
+ if (!fixed_clk)
85+
+ return -EINVAL;
86+
+
87+
+ num_clks = 0;
88+
+ for (p = fixed_clk; p->name; p++)
89+
+ num_clks++;
90+
91+
hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks + 1),
92+
GFP_KERNEL);
93+
@@ -415,7 +439,8 @@ static const struct dev_pm_ops ipq_cmn_pll_pm_ops = {
94+
};
95+
96+
static const struct of_device_id ipq_cmn_pll_clk_ids[] = {
97+
- { .compatible = "qcom,ipq9574-cmn-pll", },
98+
+ { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks },
99+
+ { .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks },
100+
{ }
101+
};
102+
MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids);
103+
--
104+
2.34.1
105+

‎target/linux/qualcommbe/patches-6.12/0603-arm64-dts-qcom-ipq5424-Add-CMN-PLL-node.patch‎

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@@ -0,0 +1,121 @@
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From 32507b97ac904e137ba6dac5938c7b450c536a54 Mon Sep 17 00:00:00 2001
2+
From: Luo Jie <quic_luoj@quicinc.com>
3+
Date: Tue, 10 Jun 2025 18:35:20 +0800
4+
Subject: [PATCH 603/636] arm64: dts: qcom: ipq5424: Add CMN PLL node
5+
6+
Add CMN PLL node for enabling output clocks to the networking
7+
hardware blocks on IPQ5424 devices.
8+
9+
The reference clock of CMN PLL is routed from XO to the CMN PLL
10+
through the internal WiFi block.
11+
.XO (48 MHZ or 96 MHZ or 192 MHZ)-->WiFi (multiplier/divider)-->
12+
48 MHZ to CMN PLL.
13+
14+
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
15+
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
16+
Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-3-ceada8165645@quicinc.com
17+
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
18+
---
19+
arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 17 +++++++++++++-
20+
arch/arm64/boot/dts/qcom/ipq5424.dtsi | 26 ++++++++++++++++++++-
21+
2 files changed, 41 insertions(+), 2 deletions(-)
22+
23+
diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
24+
index 8d9d2c1f71cc..be01c21b5919 100644
25+
--- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
26+
+++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
27+
@@ -2,7 +2,7 @@
28+
/*
29+
* IPQ5424 RDP466 board device tree source
30+
*
31+
- * Copyright (c) 2024 The Linux Foundation. All rights reserved.
32+
+ * Copyright (c) 2024-2025 The Linux Foundation. All rights reserved.
33+
*/
34+
35+
/dts-v1/;
36+
@@ -159,6 +159,21 @@
37+
status = "okay";
38+
};
39+
40+
+/*
41+
+ * The bootstrap pins for the board select the XO clock frequency that
42+
+ * supports 48 MHZ, 96 MHZ or 192 MHZ. This setting automatically
43+
+ * enables the right dividers, to ensure the reference clock output
44+
+ * from WiFi to the CMN PLL is 48 MHZ.
45+
+ */
46+
+&ref_48mhz_clk {
47+
+ clock-div = <1>;
48+
+ clock-mult = <1>;
49+
+};
50+
+
51+
&xo_board {
52+
clock-frequency = <24000000>;
53+
};
54+
+
55+
+&xo_clk {
56+
+ clock-frequency = <48000000>;
57+
+};
58+
diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
59+
index 6355153ab44e..a6cd72632817 100644
60+
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
61+
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
62+
@@ -3,10 +3,11 @@
63+
* IPQ5424 device tree source
64+
*
65+
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
66+
- * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
67+
+ * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
68+
*/
69+
70+
#include <dt-bindings/interrupt-controller/arm-gic.h>
71+
+#include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h>
72+
#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
73+
#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
74+
#include <dt-bindings/interconnect/qcom,ipq5424.h>
75+
@@ -18,6 +19,12 @@
76+
interrupt-parent = <&intc>;
77+
78+
clocks {
79+
+ ref_48mhz_clk: ref-48mhz-clk {
80+
+ compatible = "fixed-factor-clock";
81+
+ clocks = <&xo_clk>;
82+
+ #clock-cells = <0>;
83+
+ };
84+
+
85+
sleep_clk: sleep-clk {
86+
compatible = "fixed-clock";
87+
#clock-cells = <0>;
88+
@@ -27,6 +34,11 @@
89+
compatible = "fixed-clock";
90+
#clock-cells = <0>;
91+
};
92+
+
93+
+ xo_clk: xo-clk {
94+
+ compatible = "fixed-clock";
95+
+ #clock-cells = <0>;
96+
+ };
97+
};
98+
99+
cpus: cpus {
100+
@@ -205,6 +217,18 @@
101+
status = "disabled";
102+
};
103+
104+
+ cmn_pll: clock-controller@9b000 {
105+
+ compatible = "qcom,ipq5424-cmn-pll";
106+
+ reg = <0 0x0009b000 0 0x800>;
107+
+ clocks = <&ref_48mhz_clk>,
108+
+ <&gcc GCC_CMN_12GPLL_AHB_CLK>,
109+
+ <&gcc GCC_CMN_12GPLL_SYS_CLK>;
110+
+ clock-names = "ref", "ahb", "sys";
111+
+ #clock-cells = <1>;
112+
+ assigned-clocks = <&cmn_pll IPQ5424_CMN_PLL_CLK>;
113+
+ assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
114+
+ };
115+
+
116+
pcie2_phy: phy@f4000 {
117+
compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy",
118+
"qcom,ipq9574-qmp-gen3x2-pcie-phy";
119+
--
120+
2.34.1
121+

‎target/linux/qualcommbe/patches-6.12/0604-arm64-dts-qcom-Update-IPQ5424-xo_board-to-use-fixed-.patch‎

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@@ -0,0 +1,55 @@
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From 1e2feaca39efb84c0874829e214d370683880593 Mon Sep 17 00:00:00 2001
2+
From: Luo Jie <quic_luoj@quicinc.com>
3+
Date: Tue, 10 Jun 2025 18:35:21 +0800
4+
Subject: [PATCH 604/636] arm64: dts: qcom: Update IPQ5424 xo_board to use
5+
fixed factor clock
6+
7+
xo_board is fixed to 24 MHZ, which is routed from WiFi output clock
8+
48 MHZ (also being the reference clock of CMN PLL) divided 2 by
9+
analog block routing channel.
10+
11+
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
12+
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
13+
Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-4-ceada8165645@quicinc.com
14+
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
15+
---
16+
arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 7 ++++++-
17+
arch/arm64/boot/dts/qcom/ipq5424.dtsi | 3 ++-
18+
2 files changed, 8 insertions(+), 2 deletions(-)
19+
20+
diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
21+
index be01c21b5919..0705cbe33f25 100644
22+
--- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
23+
+++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
24+
@@ -170,8 +170,13 @@
25+
clock-mult = <1>;
26+
};
27+
28+
+/*
29+
+ * The frequency of xo_board is fixed to 24 MHZ, which is routed
30+
+ * from WiFi output clock 48 MHZ divided by 2.
31+
+ */
32+
&xo_board {
33+
- clock-frequency = <24000000>;
34+
+ clock-div = <2>;
35+
+ clock-mult = <1>;
36+
};
37+
38+
&xo_clk {
39+
diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
40+
index a6cd72632817..9e5120933b7e 100644
41+
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
42+
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
43+
@@ -31,7 +31,8 @@
44+
};
45+
46+
xo_board: xo-board-clk {
47+
- compatible = "fixed-clock";
48+
+ compatible = "fixed-factor-clock";
49+
+ clocks = <&ref_48mhz_clk>;
50+
#clock-cells = <0>;
51+
};
52+
53+
--
54+
2.34.1
55+

‎target/linux/qualcommbe/patches-6.12/0605-dt-bindings-net-pcs-Add-PCS-support-for-Qualcomm-IPQ.patch‎

Lines changed: 29 additions & 0 deletions
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@@ -0,0 +1,29 @@
1+
From 32e3d5fe3bb32233cf6356948ff4af9a027455c8 Mon Sep 17 00:00:00 2001
2+
From: Lei Wei <quic_leiwei@quicinc.com>
3+
Date: Tue, 18 Feb 2025 16:46:39 +0800
4+
Subject: [PATCH 605/636] dt-bindings: net: pcs: Add PCS support for Qualcomm
5+
IPQ5424 SoC.
6+
7+
Extend compatible property to support IPQ5424 PCS.
8+
9+
Change-Id: I92711e658d164e22506f5e1d26136ad4b5ae1dce
10+
Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
11+
---
12+
Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml | 1 +
13+
1 file changed, 1 insertion(+)
14+
15+
diff --git a/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml b/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml
16+
index b8049542530e..9dbf137aade1 100644
17+
--- a/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml
18+
+++ b/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml
19+
@@ -77,6 +77,7 @@ description:
20+
properties:
21+
compatible:
22+
enum:
23+
+ - qcom,ipq5424-pcs
24+
- qcom,ipq9574-pcs
25+
26+
reg:
27+
--
28+
2.34.1
29+

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