This folder contains language and compiler design notes for ez-lang.
- EeZee Programming Language - Source language overview, including syntax, types, control flow, expressions, and grammar.
- Intermediate Representations - Overview of the compiler IRs used in the project, including stack-based, register-based, and sea-of-nodes forms.
- IR Design Instructions - Notes on designing linear IRs, including basic blocks, control flow graphs, and instruction organization.
- Virtual Registers - Design discussion for virtual register representation, source variable slots, temporaries, and register identity.
- Liveness Analysis - Description of the liveness sets and algorithm used by the optimizing VM.
- SSA Construction - Explanation of SSA conversion, dominance-frontier phi placement, and register renaming.
- SSA Destruction Using Briggs - Explanation of the Briggs SSA destruction algorithm and how phi nodes are lowered to copies.