[RISC-V][PR target/123904] Improve bit masking of shifted values

If we are masking off bits on the upper and lower part of a register on riscv,
depending on the precise mask it may be best implemented as a shift triplet.
ie, shift left to clear upper bits, shift right to clear lower bits, shift left
again to put the bits into their proper position.

If the input value is already left shifted and the shift count corresponds to
the low mask bits, then we can get away with just two shifts.  We shift left to
clear the relevant high bits, then shift right to put them into their proper
position.

This likey came from spec or coremark given it was reported to me by the RAU
team a while back.  But the testcase didn't include enough breadcrumbs to know
for sure.

This has been repeatedly bootstrapped and regression tested on the Pioneer and
BPI as well as regularly regression tested on the riscv32-elf and riscv64-elf
embedded targets.

I'll wait for pre-commit CI to spin before pushing to the trunk.

	PR target/123904
gcc/
	* config/riscv/riscv.md (masking shifted value): New splitter to
	optimize certain masking operations on shifted values.

gcc/testsuite/
	* gcc.target/riscv/pr123904.c: New test.

Author: Jeff Law

gcc/config/riscv/riscv.md

@@ -5037,6 +5037,36 @@
    operands[4] = gen_lowpart (QImode, operands[3]);
  })
 
+;; This is similar using a shift triplet to implement a logical AND when
+;; the mask is a consecutive_bits_operand.
+;;
+;; The difference is we have a left shift in the input RTL and we verify
+;; that clears the appropriate low bits.  So we can get away with just
+;; two shifts.
+(define_split
+  [(set (match_operand:X 0 "register_operand")
+	(and:X (ashift:X (match_operand:X 1 "register_operand")
+			 (match_operand 2 "const_int_operand"))
+		(match_operand 3 "consecutive_bits_operand")))
+   (clobber (match_operand:X 4 "register_operand"))]
+  "(ctz_hwi (INTVAL (operands[3]) & GET_MODE_MASK (word_mode))
+    == INTVAL (operands[2]))"
+  [(set (match_dup 4) (ashift:X (match_dup 1) (match_dup 5)))
+   (set (match_dup 0) (lshiftrt:X (match_dup 4) (match_dup 6)))]
+"{
+  /* We want to left shift by the number of leading zeros in the mask,
+     plus the number of bits shifted left by the pattern.  Remember that
+     a HOST_WIDE_INT may be 64 bits, so clz on that value can count bits
+     we don't care about for rv32.  */
+  HOST_WIDE_INT lshift
+    = clz_hwi (UINTVAL (operands[3])) % BITS_PER_WORD + INTVAL (operands[2]);
+  operands[5] = gen_int_mode (lshift, QImode);
+
+  /* And then we right shift things back into position.  */
+  HOST_WIDE_INT rshift = lshift - INTVAL (operands[2]);
+  operands[6] = gen_int_mode (rshift, QImode);
+}")
+
 ;; Standard extensions and pattern for optimization
 (include "bitmanip.md")
 (include "crypto.md")

gcc/testsuite/gcc.target/riscv/pr123904.c

@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+
+unsigned foo19(unsigned a, unsigned b) { b = (b << 2) >> 2; return a + (b << 1); }
+
+/* { dg-final { scan-assembler-times "slli" 1 } } */
+/* { dg-final { scan-assembler-times "srli" 1 } } */
+/* { dg-final { scan-assembler-times "add" 1 } } */