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| 1 | +2024-01-25 Andrew Pinski <quic_apinski@quicinc.com> |
| 2 | + |
| 3 | + PR target/100204 |
| 4 | + * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT` |
| 5 | + before taking the negative of it. |
| 6 | + |
| 7 | +2024-01-25 Vladimir N. Makarov <vmakarov@redhat.com> |
| 8 | + |
| 9 | + PR target/113526 |
| 10 | + * lra-constraints.cc (curr_insn_transform): Change class even for |
| 11 | + spilled pseudo successfully matched with with NO_REGS. |
| 12 | + |
| 13 | +2024-01-25 Georg-Johann Lay <avr@gjlay.de> |
| 14 | + |
| 15 | + PR target/113601 |
| 16 | + * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start. |
| 17 | + |
| 18 | +2024-01-25 Szabolcs Nagy <szabolcs.nagy@arm.com> |
| 19 | + |
| 20 | + PR target/112987 |
| 21 | + * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New. |
| 22 | + (aarch64_expand_epilogue): Use the new function. |
| 23 | + (aarch64_split_compare_and_swap): Likewise. |
| 24 | + (aarch64_split_atomic_op): Likewise. |
| 25 | + |
| 26 | +2024-01-25 Robin Dapp <rdapp.gcc@gmail.com> |
| 27 | + |
| 28 | + PR middle-end/112971 |
| 29 | + * fold-const.cc (simplify_const_binop): New function for binop |
| 30 | + simplification of two constant vectors when element-wise |
| 31 | + handling is not necessary. |
| 32 | + (const_binop): Call new function. |
| 33 | + |
| 34 | +2024-01-25 Mary Bennett <mary.bennett@embecosm.com> |
| 35 | + |
| 36 | + * common/config/riscv/riscv-common.cc: Add XCVbitmanip. |
| 37 | + * config/riscv/constraints.md: Likewise. |
| 38 | + * config/riscv/corev.def: Likewise. |
| 39 | + * config/riscv/corev.md: Likewise. |
| 40 | + * config/riscv/predicates.md: Likewise. |
| 41 | + * config/riscv/riscv-builtins.cc (AVAIL): Likewise. |
| 42 | + * config/riscv/riscv-ftypes.def: Likewise. |
| 43 | + * config/riscv/riscv.opt: Likewise. |
| 44 | + * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'. |
| 45 | + * doc/extend.texi: Add XCVbitmanip builtin documentation. |
| 46 | + * doc/sourcebuild.texi: Likewise. |
| 47 | + |
| 48 | +2024-01-25 Tobias Burnus <tburnus@baylibre.com> |
| 49 | + |
| 50 | + * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument. |
| 51 | + |
| 52 | +2024-01-25 Yanzhang Wang <yanzhang.wang@intel.com> |
| 53 | + |
| 54 | + PR target/113538 |
| 55 | + * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag. |
| 56 | + (riscv_fntype_abi): Ditto. |
| 57 | + * config/riscv/riscv.opt: Ditto. |
| 58 | + |
| 59 | +2024-01-25 Jakub Jelinek <jakub@redhat.com> |
| 60 | + |
| 61 | + PR middle-end/113574 |
| 62 | + * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift |
| 63 | + count against TYPE_PRECISION rather than TYPE_SIZE. |
| 64 | + |
| 65 | +2024-01-25 Richard Sandiford <richard.sandiford@arm.com> |
| 66 | + |
| 67 | + PR target/113572 |
| 68 | + * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same): |
| 69 | + Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT |
| 70 | + |
| 71 | +2024-01-25 Richard Sandiford <richard.sandiford@arm.com> |
| 72 | + |
| 73 | + PR target/113550 |
| 74 | + * config/aarch64/aarch64-simd.md: In the movv8di splitter, check |
| 75 | + whether each split instruction is a load that clobbers the source |
| 76 | + address. Emit that instruction last if so. |
| 77 | + |
| 78 | +2024-01-25 Richard Sandiford <richard.sandiford@arm.com> |
| 79 | + |
| 80 | + PR target/113485 |
| 81 | + * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New |
| 82 | + pattern. |
| 83 | + (<optab><Vnarrowq><mode>2): Use it instead of generating a |
| 84 | + paradoxical subreg for the input. |
| 85 | + |
| 86 | +2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai> |
| 87 | + |
| 88 | + * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function. |
| 89 | + (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all |
| 90 | + predecessors dump information. |
| 91 | + |
| 92 | +2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai> |
| 93 | + |
| 94 | + * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove |
| 95 | + redundant full available computation. |
| 96 | + (pre_vsetvl::pre_global_vsetvl_info): Ditto. |
| 97 | + |
| 98 | +2024-01-25 Jakub Jelinek <jakub@redhat.com> |
| 99 | + |
| 100 | + * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns. |
| 101 | + * doc/rtl.texi (CONST_VECTOR): Likewise. |
| 102 | + |
| 103 | +2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai> |
| 104 | + |
| 105 | + * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option. |
| 106 | + * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto. |
| 107 | + (pass_vsetvl::execute): Ditto. |
| 108 | + * config/riscv/riscv.opt: Ditto. |
| 109 | + |
| 110 | +2024-01-25 Jiahao Xu <xujiahao@loongson.cn> |
| 111 | + |
| 112 | + * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern. |
| 113 | + * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>. |
| 114 | + |
| 115 | +2024-01-25 Richard Biener <rguenther@suse.de> |
| 116 | + |
| 117 | + PR tree-optimization/113576 |
| 118 | + * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow |
| 119 | + exits with may_be_zero niters when its the last one. |
| 120 | + |
| 121 | +2024-01-25 Lulu Cheng <chenglulu@loongson.cn> |
| 122 | + |
| 123 | + * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p): |
| 124 | + For symbols of type tls, non-zero Offset is not generated. |
| 125 | + |
| 126 | +2024-01-25 Haochen Gui <guihaoc@gcc.gnu.org> |
| 127 | + |
| 128 | + * config/rs6000/rs6000-string.cc (expand_block_compare): Enable |
| 129 | + P9 with m32 and mpowerpc64. |
| 130 | + |
| 131 | +2024-01-25 liuhongt <hongtao.liu@intel.com> |
| 132 | + |
| 133 | + * config/i386/i386-options.cc (ix86_option_override_internal): |
| 134 | + Enable -mlam=u57 by default when compiled with |
| 135 | + -fsanitize=hwaddress. |
| 136 | + |
| 137 | +2024-01-25 Palmer Dabbelt <palmer@rivosinc.com> |
| 138 | + |
| 139 | + * common/config/riscv/riscv-common.cc (riscv_implied_info): |
| 140 | + Remove {"ztso", "a"}. |
| 141 | + |
1 | 142 | 2024-01-24 Martin Jambor <mjambor@suse.cz> |
2 | 143 |
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3 | 144 | PR ipa/108007 |
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