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aarch64: Add initial tuning model for cortex-a320 core
gcc/ChangeLog: * config/aarch64/aarch64-cores.def (cortex-a320): Update core. * config/aarch64/aarch64.cc: Add cortexa320.h. * config/aarch64/tuning_models/cortexa320.h: New file.
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‎gcc/config/aarch64/aarch64-cores.def‎

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@@ -217,7 +217,7 @@ AARCH64_CORE("cortex-a720", cortexa720, cortexa57, V9_2A, (SVE2_BITPERM, MEMTA
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AARCH64_CORE("cortex-a720ae", cortexa720ae, cortexa57, V9_2A, (SVE2_BITPERM, MEMTAG, PROFILE), neoversen2, 0x41, 0xd89, -1)
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AARCH64_CORE("cortex-a725", cortexa725, cortexa57, V9_2A, (SVE2_BITPERM, MEMTAG, PROFILE), neoversen3, 0x41, 0xd87, -1)
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AARCH64_CORE("cortex-a320", cortexa320, cortexa53, V9_2A, (SVE2_BITPERM, MEMTAG), cortexa53, 0x41, 0xd8f, -1)
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AARCH64_CORE("cortex-a320", cortexa320, cortexa53, V9_2A, (SVE2_BITPERM, MEMTAG), cortexa320, 0x41, 0xd8f, -1)
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AARCH64_CORE("cortex-x2", cortexx2, cortexa57, V9A, (SVE2_BITPERM, MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd48, -1)
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‎gcc/config/aarch64/aarch64.cc‎

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@@ -416,6 +416,7 @@ static const struct aarch64_flag_desc aarch64_tuning_flags[] =
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#include "tuning_models/generic.h"
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#include "tuning_models/generic_armv8_a.h"
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#include "tuning_models/generic_armv9_a.h"
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#include "tuning_models/cortexa320.h"
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#include "tuning_models/cortexa35.h"
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#include "tuning_models/cortexa53.h"
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#include "tuning_models/cortexa57.h"

‎gcc/config/aarch64/tuning_models/cortexa320.h‎

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/* Tuning model description for AArch64 architecture.
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Copyright (C) 2009-2026 Free Software Foundation, Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#ifndef GCC_AARCH64_H_CORTEXA320
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#define GCC_AARCH64_H_CORTEXA320
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#include "generic.h"
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static const struct cpu_addrcost_table cortexa320_addrcost_table =
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{
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{
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1, /* hi */
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0, /* si */
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0, /* di */
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1, /* ti */
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},
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0, /* pre_modify */
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0, /* post_modify */
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2, /* post_modify_ld3_st3 */
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2, /* post_modify_ld4_st4 */
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0, /* register_offset */
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0, /* register_sextend */
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0, /* register_zextend */
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0 /* imm_offset */
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};
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static const struct cpu_regmove_cost cortexa320_regmove_cost =
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{
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1, /* GP2GP */
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/* Avoid the use of slow int<->fp moves for spilling by setting
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their cost higher than memmov_cost. */
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5, /* GP2FP */
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5, /* FP2GP */
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2 /* FP2FP */
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};
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static const advsimd_vec_cost cortexa320_advsimd_vector_cost =
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{
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3, /* int_stmt_cost */
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4, /* fp_stmt_cost */
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1, /* ld2_st2_permute_cost */
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2, /* ld3_st3_permute_cost */
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3, /* ld4_st4_permute_cost */
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3, /* permute_cost */
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3, /* reduc_i8_cost */
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4, /* reduc_i16_cost */
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4, /* reduc_i32_cost */
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3, /* reduc_i64_cost */
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12, /* reduc_f16_cost */
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8, /* reduc_f32_cost */
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4, /* reduc_f64_cost */
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0, /* store_elt_extra_cost */
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/* This value is just inherited from the Cortex-A57 table. */
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8, /* vec_to_scalar_cost */
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/* This depends very much on what the scalar value is and
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where it comes from. E.g. some constants take two dependent
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instructions or a load, while others might be moved from a GPR.
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4 seems to be a reasonable compromise in practice. */
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4, /* scalar_to_vec_cost */
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5, /* align_load_cost */
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5, /* unalign_load_cost */
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/* Although stores have a latency of 2 and compete for the
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vector pipes, in practice it's better not to model that. */
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2, /* unalign_store_cost */
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2 /* store_cost */
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};
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static const sve_vec_cost cortexa320_sve_vector_cost =
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{
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{
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3, /* int_stmt_cost */
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4, /* fp_stmt_cost */
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1, /* ld2_st2_permute_cost */
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2, /* ld3_st3_permute_cost */
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3, /* ld4_st4_permute_cost */
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3, /* permute_cost */
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/* Theoretically, a reduction involving 15 scalar ADDs could
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complete in ~15 cycles and would have a cost of 15. [SU]ADDV
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completes in 4 cycles, so give it a cost of 15 + -11. */
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4, /* reduc_i8_cost */
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/* Likewise for 7 scalar ADDs (~7 cycles) vs. 4: 7 + -3. */
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4, /* reduc_i16_cost */
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/* Likewise for 3 scalar ADDs (~3 cycles) vs. 4: 3 + 1. */
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4, /* reduc_i32_cost */
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/* Likewise for 1 scalar ADD (~1 cycles) vs. 4: 1 + 3. */
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4, /* reduc_i64_cost */
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/* Theoretically, a reduction involving 7 scalar FADDs could
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complete in ~28 cycles and would have a cost of 28. FADDV
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completes in 12 cycles, so give it a cost of 28 + -16. */
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12, /* reduc_f16_cost */
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/* Likewise for 3 scalar FADDs (~12 cycles) vs. 8: 12 + -4. */
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8, /* reduc_f32_cost */
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/* Likewise for 1 scalar FADD (~4 cycles) vs. 4: 4 + 0. */
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4, /* reduc_f64_cost */
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0, /* store_elt_extra_cost */
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/* This value is just inherited from the Cortex-A57 table. */
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8, /* vec_to_scalar_cost */
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/* See the comment above the Advanced SIMD versions. */
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4, /* scalar_to_vec_cost */
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5, /* align_load_cost */
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5, /* unalign_load_cost */
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/* Although stores have a latency of 2 and compete for the
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vector pipes, in practice it's better not to model that. */
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2, /* unalign_store_cost */
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2 /* store_cost */
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},
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4, /* clast_cost */
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25, /* fadda_f16_cost */
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9, /* fadda_f32_cost */
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3, /* fadda_f64_cost */
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/* A strided Advanced SIMD x64 load would take two parallel FP loads
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(10 cycles) plus an insertion (3 cycles). Assume a 64-bit SVE gather
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is 1 cycle more. The Advanced SIMD version is costed as 2 scalar loads
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(cost 10) and a vec_construct (cost 3). Add a full vector operation
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(cost 3) to that, to avoid the difference being lost in rounding.
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There is no easy comparison between a strided Advanced SIMD x32 load
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and an SVE 32-bit gather, but cost an SVE 32-bit gather as 1 vector
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operation more than a 64-bit gather. */
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16, /* gather_load_x32_cost */
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19, /* gather_load_x64_cost */
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48, /* gather_load_x32_init_cost */
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38, /* gather_load_x64_init_cost */
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0 /* scatter_store_elt_cost */
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};
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/* Cortexa320 costs for vector insn classes. */
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static const struct cpu_vector_cost cortexa320_vector_cost =
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{
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1, /* scalar_int_stmt_cost */
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2, /* scalar_fp_stmt_cost */
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4, /* scalar_load_cost */
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1, /* scalar_store_cost */
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1, /* cond_taken_branch_cost */
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1, /* cond_not_taken_branch_cost */
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&cortexa320_advsimd_vector_cost, /* advsimd */
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&cortexa320_sve_vector_cost, /* sve */
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nullptr /* issue_info */
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};
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static const struct tune_params cortexa320_tunings =
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{
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&cortexa76_extra_costs,
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&cortexa320_addrcost_table,
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&cortexa320_regmove_cost,
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&cortexa320_vector_cost,
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&generic_branch_cost,
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&generic_approx_modes,
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SVE_128, /* sve_width */
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{ 4, /* load_int. */
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1, /* store_int. */
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5, /* load_fp. */
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2, /* store_fp. */
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4, /* load_pred. */
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1 /* store_pred. */
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}, /* memmov_cost. */
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1, /* issue_rate */
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AARCH64_FUSE_NEOVERSE_BASE, /* fusible_ops */
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"32:16", /* function_align. */
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"4", /* jump_align. */
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"32:16", /* loop_align. */
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2, /* int_reassoc_width. */
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4, /* fp_reassoc_width. */
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1, /* fma_reassoc_width. */
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2, /* vec_reassoc_width. */
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2, /* min_div_recip_mul_sf. */
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2, /* min_div_recip_mul_df. */
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0, /* max_case_values. */
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tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */
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(AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND
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| AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS
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| AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT), /* tune_flags. */
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&generic_armv9a_prefetch_tune,
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AARCH64_LDP_STP_POLICY_ALWAYS, /* ldp_policy_model. */
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AARCH64_LDP_STP_POLICY_ALWAYS, /* stp_policy_model. */
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nullptr /* dispatch_constraints. */
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};
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#endif /* GCC_AARCH64_H_CORTEXA320. */

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