@@ -22,112 +22,112 @@ static alignas(32) char buf2[BUF_SIZE];
2222
2323static void dma_done (void * d )
2424{
25- * (uint64_t * )d = timer_us_gettime64 ();
26- genwait_wake_all (d );
25+ * (uint64_t * )d = timer_us_gettime64 ();
26+ genwait_wake_all (d );
2727}
2828
2929static dma_config_t dma_cfg = {
30- .channel = 1 ,
31- .request = DMA_REQUEST_AUTO_MEM_TO_MEM ,
32- .unit_size = DMA_UNITSIZE_32BYTE ,
33- .src_mode = DMA_ADDRMODE_INCREMENT ,
34- .dst_mode = DMA_ADDRMODE_INCREMENT ,
35- .transmit_mode = DMA_TRANSMITMODE_BURST ,
36- .callback = dma_done ,
30+ .channel = 1 ,
31+ .request = DMA_REQUEST_AUTO_MEM_TO_MEM ,
32+ .unit_size = DMA_UNITSIZE_32BYTE ,
33+ .src_mode = DMA_ADDRMODE_INCREMENT ,
34+ .dst_mode = DMA_ADDRMODE_INCREMENT ,
35+ .transmit_mode = DMA_TRANSMITMODE_BURST ,
36+ .callback = dma_done ,
3737};
3838
3939static uint64_t
4040do_dma_transfer (unsigned int test , pvr_ptr_t vram1 , pvr_ptr_t vram2 )
4141{
42- uint64_t before , after = 0 ;
43-
44- irq_disable_scoped ();
45-
46- before = timer_us_gettime64 ();
47-
48- switch (test ) {
49- case 0 :
50- /* RAM to RAM */
51- dma_transfer (& dma_cfg ,
52- dma_map_dst (buf1 , BUF_SIZE ),
53- dma_map_src (buf2 , BUF_SIZE ),
54- BUF_SIZE , & after );
55- break ;
56- case 1 :
57- /* RAM to VRAM */
58- dma_transfer (& dma_cfg ,
59- hw_to_dma_addr ((uintptr_t )vram1 ),
60- dma_map_src (buf2 , BUF_SIZE ),
61- BUF_SIZE , & after );
62- break ;
63- case 2 :
64- /* VRAM to RAM */
65- dma_transfer (& dma_cfg ,
66- dma_map_dst (buf1 , BUF_SIZE ),
67- hw_to_dma_addr ((uintptr_t )vram1 ),
68- BUF_SIZE , & after );
69- break ;
70- case 3 :
71- /* VRAM to VRAM */
72- dma_transfer (& dma_cfg ,
73- hw_to_dma_addr ((uintptr_t )vram1 ),
74- hw_to_dma_addr ((uintptr_t )vram2 ),
75- BUF_SIZE , & after );
76- break ;
77- case 4 :
78- /* RAM to VRAM using SQs */
79- pvr_txr_load (buf1 , vram1 , BUF_SIZE );
80-
81- return timer_us_gettime64 () - before ;
82- case 5 :
83- /* RAM to 64-bit VRAM using PVR DMA */
84- pvr_txr_load_dma (buf1 , vram1 , BUF_SIZE ,
85- 0 , dma_done , & after );
86- break ;
87- case 6 :
88- /* RAM to 32-bit VRAM using PVR DMA */
89- pvr_dma_transfer (buf1 , (uintptr_t )vram1 , BUF_SIZE ,
90- PVR_DMA_VRAM32 , 0 ,
91- dma_done , & after );
92- break ;
93- }
94-
95- while ((volatile uint64_t )after == 0 )
96- genwait_wait (& after , "IRQ wait" , 0 , NULL );
97-
98- return after - before ;
42+ uint64_t before , after = 0 ;
43+
44+ irq_disable_scoped ();
45+
46+ before = timer_us_gettime64 ();
47+
48+ switch (test ) {
49+ case 0 :
50+ /* RAM to RAM */
51+ dma_transfer (& dma_cfg ,
52+ dma_map_dst (buf1 , BUF_SIZE ),
53+ dma_map_src (buf2 , BUF_SIZE ),
54+ BUF_SIZE , & after );
55+ break ;
56+ case 1 :
57+ /* RAM to VRAM */
58+ dma_transfer (& dma_cfg ,
59+ hw_to_dma_addr ((uintptr_t )vram1 ),
60+ dma_map_src (buf2 , BUF_SIZE ),
61+ BUF_SIZE , & after );
62+ break ;
63+ case 2 :
64+ /* VRAM to RAM */
65+ dma_transfer (& dma_cfg ,
66+ dma_map_dst (buf1 , BUF_SIZE ),
67+ hw_to_dma_addr ((uintptr_t )vram1 ),
68+ BUF_SIZE , & after );
69+ break ;
70+ case 3 :
71+ /* VRAM to VRAM */
72+ dma_transfer (& dma_cfg ,
73+ hw_to_dma_addr ((uintptr_t )vram1 ),
74+ hw_to_dma_addr ((uintptr_t )vram2 ),
75+ BUF_SIZE , & after );
76+ break ;
77+ case 4 :
78+ /* RAM to VRAM using SQs */
79+ pvr_txr_load (buf1 , vram1 , BUF_SIZE );
80+
81+ return timer_us_gettime64 () - before ;
82+ case 5 :
83+ /* RAM to 64-bit VRAM using PVR DMA */
84+ pvr_txr_load_dma (buf1 , vram1 , BUF_SIZE ,
85+ 0 , dma_done , & after );
86+ break ;
87+ case 6 :
88+ /* RAM to 32-bit VRAM using PVR DMA */
89+ pvr_dma_transfer (buf1 , (uintptr_t )vram1 , BUF_SIZE ,
90+ PVR_DMA_VRAM32 , 0 ,
91+ dma_done , & after );
92+ break ;
93+ }
94+
95+ while ((volatile uint64_t )after == 0 )
96+ genwait_wait (& after , "IRQ wait" , 0 , NULL );
97+
98+ return after - before ;
9999}
100100
101101static const char * const test_lbl [] = {
102- "DMAC, RAM to RAM: " ,
103- "DMAC, RAM to VRAM: " ,
104- "DMAC, VRAM to RAM: " ,
105- "DMAC, VRAM to VRAM: " ,
106- "PVR SQs: " ,
107- "PVR DMA, 64-bit: " ,
108- "PVR DMA, 32-bit: " ,
102+ "DMAC, RAM to RAM: " ,
103+ "DMAC, RAM to VRAM: " ,
104+ "DMAC, VRAM to RAM: " ,
105+ "DMAC, VRAM to VRAM: " ,
106+ "PVR SQs: " ,
107+ "PVR DMA, 64-bit: " ,
108+ "PVR DMA, 32-bit: " ,
109109};
110110
111111int main (int argc , char * * argv )
112112{
113- pvr_ptr_t vram , vram2 ;
114- uint64_t time_us ;
115- unsigned int i ;
113+ pvr_ptr_t vram , vram2 ;
114+ uint64_t time_us ;
115+ unsigned int i ;
116116
117- pvr_init_defaults ();
117+ pvr_init_defaults ();
118118
119- vram = pvr_mem_malloc (BUF_SIZE );
120- vram2 = pvr_mem_malloc (BUF_SIZE );
119+ vram = pvr_mem_malloc (BUF_SIZE );
120+ vram2 = pvr_mem_malloc (BUF_SIZE );
121121
122- for (i = 0 ; i < ARRAY_SIZE (test_lbl ); i ++ ) {
123- time_us = do_dma_transfer (i , vram , vram2 );
124- printf ("%s%f MiB/s\n" ,
125- test_lbl [i ], (float )BUF_SIZE / (float )time_us );
122+ for (i = 0 ; i < ARRAY_SIZE (test_lbl ); i ++ ) {
123+ time_us = do_dma_transfer (i , vram , vram2 );
124+ printf ("%s%f MiB/s\n" ,
125+ test_lbl [i ], (float )BUF_SIZE / (float )time_us );
126126
127- }
127+ }
128128
129- pvr_mem_free (vram );
130- pvr_mem_free (vram2 );
129+ pvr_mem_free (vram );
130+ pvr_mem_free (vram2 );
131131
132- return 0 ;
132+ return 0 ;
133133}
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