aica: Enhanced driver initialization.

Updated the AICA initialization routine to include additional setup for interrupt sources and FIQ handling.
This is a sound fix for NAOMI and NAOMI 2 systems running BIOS without startup sound, as well as for Dreamcast on stock BIOS when returning to KOS from another SDK.

Author: DC-SWAT

kernel/arch/dreamcast/sound/arm/aica.c

@@ -3,6 +3,7 @@
    aica.c
    (c)2000-2002 Megan Potter
    (c)2024 Stefanos Kornilios Mitsis Poiitidis
+   (c)2026 Ruslan Rostovtsev
 
    ARM support routines for using the wavetable channels
 */
@@ -11,13 +12,26 @@
 #include "aica.h"
 
 extern volatile aica_channel_t *chans;
+extern void arm_fiq_enable(void);
 
 void aica_init(void) {
     int i, j;
 
-    /* Initialize AICA channels */
+    /* SCIEB/MCIEB: mask all interrupt sources during setup. */
+    SNDREG32(0x289C) = 0;
+    SNDREG32(0x28B4) = 0;
+    /* SCIRE/MCIRE: acknowledge pending Sound/Main CPU interrupts. */
+    SNDREG32(0x28A4) = 0x7FF;
+    SNDREG32(0x28BC) = 0x7FF;
+    /* SCILV0/1/2: deliver AICA events on FIQ (used by fiq_timer in crt0.s). */
+    SNDREG32(0x28A8) = 0x18;
+    SNDREG32(0x28AC) = 0x50;
+    SNDREG32(0x28B0) = 0x08;
+
+    /* Drop master volume while channel registers are cleared. */
     SNDREG32(0x2800) = 0x0000;
 
+    /* Initialize AICA channels */
     for(i = 0; i < 64; i++) {
         CHNREG32(i, 0) = 0x8000;
 
@@ -27,7 +41,15 @@ void aica_init(void) {
         CHNREG32(i, 20) = 0x1f;
     }
 
+    /* Restore default mixer routing after channel reset. */
     SNDREG32(0x2800) = 0x000f;
+    /* Timer A reload (same as crt0.s). */
+    SNDREG32(0x2890) = 256 - (44100 / 4410);
+    /* SCIEB bit 6: unmask Timer A as the sole FIQ source. */
+    SNDREG32(0x289C) = 0x40;
+
+    /* Unmask FIQ in CPSR once Timer A and SCILV are configured. */
+    arm_fiq_enable();
 }
 
 /* Translates a volume from linear form to logarithmic form (required by

kernel/arch/dreamcast/sound/arm/crt0.s

@@ -2,12 +2,14 @@
 #
 #  crt0.s
 #  (c)2000-2002 Megan Potter
+#  (c)2026 Ruslan Rostovtsev
 #
 #  Startup for ARM program
 #  Adapted from Marcus' AICA example among a few other sources =)
 
 .text
 .globl	arm_main
+.globl	arm_fiq_enable
 .globl	jps
 
 # Meaningless but makes the linker shut up
@@ -104,14 +106,16 @@ jps:
 	# 1000 jiffies per second
 	.long	256-(44100/1000)
 
+arm_fiq_enable:
+	mrs	r0, CPSR
+	orr	r0, r0, #0x80
+	bic	r0, r0, #0x40
+	msr	CPSR_c, r0
+	mov	pc, lr
 
 start:
-	# Setup a basic stack, disable IRQ, enable FIQ
+	# Setup a basic stack, disable IRQ
 	mov	sp,#0xb000
-	mrs	r10,CPSR
-	orr	r10,r10,#0x80
-	bic	r10,r10,#0x40
-	msr	CPSR_all,r10
 
 	# Call the main for the SPU
 	bl	arm_main