hmm

Author: DarkFire01

boot/bootdata/livecd.inf

@@ -27,6 +27,14 @@ HKLM,"SYSTEM\CurrentControlSet\Services\Cdrom","Start",0x00010001,0x00000000
 ; KDB. Off for the automated benchmark image.
 HKLM,"SYSTEM\CurrentControlSet\Services\i8042prt\Parameters","CrashOnCtrlScroll",0x00010001,0x00000000
 
+; Disable the i8042 (PS/2) driver entirely (Start = SERVICE_DISABLED = 4). This q35
+; board has an i8042 controller with NO PS/2 keyboard/mouse attached (input is via
+; USB-HID), so the controller emits spurious interrupts/scancodes that intermittently
+; crash i8042prt during init (e.g. ASSERT ControlPort!=NULL in i8042ReadStatus, or the
+; SYSRQ break) -- a major source of flaky SMP boot. The USB keyboard is unaffected.
+HKLM,"SYSTEM\CurrentControlSet\Services\i8042prt","Start",0x00010001,0x00000004
+HKLM,"SYSTEM\CurrentControlSet\Services\i8042prt","DependOnService",0x00010000,""
+
 ; Reset BootExecute to an empty value: AutoChk should not start in MiniNT mode
 HKLM,"SYSTEM\CurrentControlSet\Control\Session Manager","BootExecute",0x00010000,""
 

drivers/input/i8042prt/registry.c

@@ -6,7 +6,7 @@
  * PROGRAMMERS: Copyright Victor Kirhenshtein (sauros@iname.com)
                 Copyright Jason Filby (jasonfilby@yahoo.com)
                 Copyright Martijn Vernooij (o112w8r02@sneakemail.com)
-                Copyright 2006-2007 Hervé Poussineau (hpoussin@reactos.org)
+                Copyright 2006-2007 Herv� Poussineau (hpoussin@reactos.org)
  */
 
 /* INCLUDES ******************************************************************/
@@ -41,14 +41,13 @@ ReadRegistryEntries(
 	ULONG DefaultSampleRate = 60;
 	ULONG DefaultCrashOnCtrlScroll;
 
-	/* Default value for CrashOnCtrlScroll depends if we're
-	 * running a debug build or a normal build.
-	 */
-#if DBG
-	DefaultCrashOnCtrlScroll = 1;
-#else
+	/* Default value for CrashOnCtrlScroll. Normally ON in debug builds, but on
+	 * this branch the q35 board has an i8042 controller with no PS/2 keyboard
+	 * attached (we use USB), so it feeds spurious scancodes that intermittently
+	 * match the TAB+k / Ctrl+ScrollLock debug-break sequence and drop an
+	 * unattended boot into KDB. Default it OFF so a stray byte can't crash boot;
+	 * the registry value (livecd.inf) can still override. */
 	DefaultCrashOnCtrlScroll = 0;
-#endif
 
 	RtlZeroMemory(Parameters, sizeof(Parameters));
 

hal/halx86/apic/rtctimer.c

@@ -21,7 +21,9 @@
 
 static const UCHAR RtcMinimumClockRate = 6;  /* Minimum rate  6: 1024 Hz / 0.97 ms */
 static const UCHAR RtcMaximumClockRate = 10; /* Maximum rate 10: 64 Hz / 15.6 ms */
-static UCHAR HalpCurrentClockRate = 6;   /* Initial rate   6: 1024 Hz / 0.977 ms.
+static UCHAR HalpCurrentClockRate = 6;   /* rate 6: 1024 Hz / 0.977 ms. (Confirmed the
+    clock rate is NOT the cause of flaky SMP boot -- 64Hz fails the same way -- so kept
+    at 1024Hz for the fine Sleep resolution.)
     NOTE: rate 5 (2048Hz) gives slightly finer Sleep (~1.45ms vs ~1.93ms) but
     REPRODUCIBLY blows up thread create+join to ~16ms (vs 59us at 1024Hz) -- the
     2x clock-IPI/interrupt load starves the thread-reaper/scheduling round-trips.
@@ -38,6 +40,7 @@ static ULONG HalpCurrentFractionalIncrement;
 static ULONG HalpRunningFraction;
 static BOOLEAN HalpSetClockRate;
 static UCHAR HalpNextClockRate;
+static ULONG HalpClockIpiAccumulator;   /* paces the AP clock-IPI to the logical tick */
 
 /*!
     \brief Converts the CMOS RTC rate into the time increment in 0.1ns intervals.
@@ -201,8 +204,20 @@ HalpClockInterruptHandler(IN PKTRAP_FRAME TrapFrame)
         HalpSetClockRate = FALSE;
     }
 
-    /* Send the clock IPI to all other CPUs */
-    HalpBroadcastClockIpi(CLOCK_IPI_VECTOR);
+    /* Send the clock IPI to the other CPUs only at the LOGICAL tick rate, not on
+     * every fine-grained 1024Hz interrupt. The APs run KeUpdateRunTime per IPI
+     * (quantum + per-tick CPU-time accounting); broadcasting at the full 1024Hz
+     * decremented AP quanta ~16x too fast (inconsistent with CPU0, which only does
+     * KeUpdateRunTime once per accumulated full tick) AND flooded the IPI path,
+     * which intermittently crashed boot once the APs were up. Accumulate the
+     * per-interrupt increment and broadcast once per HalpMaximumTimeIncrement so
+     * APs tick at the same ~64Hz logical rate as CPU0. */
+    HalpClockIpiAccumulator += LastIncrement;
+    if (HalpClockIpiAccumulator >= HalpMaximumTimeIncrement)
+    {
+        HalpClockIpiAccumulator -= HalpMaximumTimeIncrement;
+        HalpBroadcastClockIpi(CLOCK_IPI_VECTOR);
+    }
 
     /* Update the system time -- on x86 the kernel will exit this trap  */
     KeUpdateSystemTime(TrapFrame, LastIncrement, Irql);

ntoskrnl/ke/amd64/stubs.c

@@ -133,9 +133,7 @@ KiIdleLoop(VOID)
 
 #ifdef CONFIG_SMP
         /* Nothing scheduled for us? Pull a ready thread off a busier CPU rather
-         * than halting while runnable work sits elsewhere. This provides the
-         * load-balancing ReactOS otherwise lacks (placement happens once, at
-         * thread-ready time, with no later migration). */
+         * than halting while runnable work sits elsewhere (load-balancing). */
         if (!Prcb->NextThread)
         {
             KiStealReadyThread(Prcb);

ntoskrnl/ke/time.c

@@ -82,16 +82,21 @@ KeUpdateSystemTime(IN PKTRAP_FRAME TrapFrame,
     /* Update the tick offset */
     OldTickOffset = InterlockedExchangeAdd(&KiTickOffset, -(LONG)Increment);
 
-    /* If the debugger is enabled, check for break-in request */
-    if (KdDebuggerEnabled && KdPollBreakIn())
-    {
-        /* Break-in requested! */
-        DbgBreakPointWithStatus(DBG_STATUS_CONTROL_C);
-    }
-
     /* Check for full tick */
     if (OldTickOffset <= (LONG)Increment)
     {
+        /* If the debugger is enabled, check for break-in request. This is done
+         * only once per logical tick (~64Hz), NOT on every fine-grained clock
+         * interrupt: at 1024Hz, polling the debug port 16x more often
+         * intermittently misreads a spurious break-in over the serial line and
+         * drops to KDB ("embedded INT3" via DbgBreakPointWithStatus), which was
+         * the most common SMP-boot crash after the timer rate was raised. */
+        if (KdDebuggerEnabled && KdPollBreakIn())
+        {
+            /* Break-in requested! */
+            DbgBreakPointWithStatus(DBG_STATUS_CONTROL_C);
+        }
+
         /* Update the system time */
         CurrentTime.QuadPart = *(ULONGLONG*)&SharedUserData->SystemTime;
         CurrentTime.QuadPart += KeTimeAdjustment;