continue bring up

Author: DarkFire01

boot/bootdata/hivesys.inf

@@ -348,6 +348,21 @@ HKLM,"SYSTEM\CurrentControlSet\Control\Arbiters\ReservedResources","PCStandard",
 00,03,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,0a,00,00,00,00,00,ff,ff,0b,00,00,00,00,00,\
 08,03,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,f0,ff,00,00,00,00,ff,ff,ff,ff,00,00,00,00
 
+; "BrokenVideo" reserved-resource profile, used by the PCI bus driver's broken
+; video hack (ario_ApplyBrokenVideoHack) for old VGA cards that positively
+; decode the full legacy VGA I/O range.  It is "PCStandard" with the two VGA
+; I/O ranges (0x3B0-0x3BB and 0x3C0-0x3DF) removed, so those ports stay in the
+; allocatable pool and can be granted to the broken video device.  COM1/COM2/LPT
+; and the legacy memory ranges remain reserved.  (5 descriptors, ListSize 0xC8.)
+HKLM,"SYSTEM\CurrentControlSet\Control\Arbiters\ReservedResources","BrokenVideo",0x000a0001,\
+c8,00,00,00,00,00,00,00,\
+00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,01,00,00,00,01,00,01,00,05,00,00,00,\
+00,01,00,00,00,00,00,00,00,00,00,00,00,00,00,00,f8,02,00,00,00,00,00,00,ff,02,00,00,00,00,00,00,\
+08,01,00,00,00,00,00,00,00,00,00,00,00,00,00,00,bc,03,00,00,00,00,00,00,be,03,00,00,00,00,00,00,\
+08,01,00,00,00,00,00,00,00,00,00,00,00,00,00,00,f8,03,00,00,00,00,00,00,ff,03,00,00,00,00,00,00,\
+00,03,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,0a,00,00,00,00,00,ff,ff,0b,00,00,00,00,00,\
+08,03,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,f0,ff,00,00,00,00,ff,ff,ff,ff,00,00,00,00
+
 HKLM,"SYSTEM\CurrentControlSet\Control\FileSystem","NtfsDisable8dot3NameCreation",0x00010003,0
 HKLM,"SYSTEM\CurrentControlSet\Control\FileSystem","NtfsMftZoneReservation",0x00010003,1
 HKLM,"SYSTEM\CurrentControlSet\Control\FileSystem","Win31FileSystem",0x00010001,0

drivers/bus/pcix/arb/ar_busno.c

@@ -194,7 +194,6 @@ arbusno_Constructor(IN PVOID DeviceExtension,
         {
             /* Not yet implemented */
             UNIMPLEMENTED;
-            while (TRUE);
         }
         else
         {

drivers/bus/pcix/arb/ar_memio.c

@@ -198,8 +198,8 @@ NTAPI
 ario_ApplyBrokenVideoHack(IN PPCI_FDO_EXTENSION FdoExtension)
 {
     PPCI_ARBITER_INSTANCE PciArbiter;
-    //PARBITER_INSTANCE CommonInstance;
-    //NTSTATUS Status;
+    PARBITER_INSTANCE CommonInstance;
+    NTSTATUS Status;
 
     /* Only valid for root FDOs who are being applied the hack for the first time */
     ASSERT(!FdoExtension->BrokenVideoHackApplied);
@@ -210,25 +210,45 @@ ario_ApplyBrokenVideoHack(IN PPCI_FDO_EXTENSION FdoExtension)
                                                       SecondaryExtension.Next,
                                                       PciArb_Io);
     ASSERT(PciArbiter);
-#if 0 // when arb exist
+    if (!PciArbiter) return;
+
     /* Get the Arb instance */
     CommonInstance = &PciArbiter->CommonInstance;
 
-    /* Free the two lists, enabling full VGA access */
-    ArbFreeOrderingList(&CommonInstance->OrderingList);
-    ArbFreeOrderingList(&CommonInstance->ReservedList);
-
-    /* Build the ordering for broken video PCI access */
+    /*
+     * Rebuild the I/O arbiter's assignment ordering using the "BrokenVideo"
+     * reserved-resource profile in place of the normal "Pci" one.  The standard
+     * profile reserves (holds back) the legacy VGA I/O ranges 0x3B0-0x3BB and
+     * 0x3C0-0x3DF so they are not handed out during arbitration; the BrokenVideo
+     * profile deliberately omits them, leaving those ranges in the allocatable
+     * pool.  That lets an old video card which positively decodes the full VGA
+     * I/O range (PCI_HACK_VIDEO_LEGACY_DECODE) actually be granted them instead
+     * of being denied and forced into a fallback.
+     *
+     * ArbBuildAssignmentOrdering frees and reinitializes the OrderingList and
+     * ReservedList itself, so there is no need to free them here first.
+     */
     Status = ArbBuildAssignmentOrdering(CommonInstance,
                                         L"Pci",
                                         L"BrokenVideo",
                                         NULL);
-    ASSERT(NT_SUCCESS(Status));
-#else
-    //Status = STATUS_SUCCESS;
-    UNIMPLEMENTED;
-    while (TRUE);
-#endif
+    if (!NT_SUCCESS(Status))
+    {
+        /* On failure ArbBuildAssignmentOrdering leaves BOTH ordering lists
+           freed/empty, which would break I/O arbitration for the whole root
+           bus.  Restore the normal "Pci" ordering (the same profile the arbiter
+           was initialized with) so the bus keeps working, and skip the hack. */
+        DPRINT1("PCI: ario_ApplyBrokenVideoHack - ArbBuildAssignmentOrdering "
+                "failed (0x%08lx); is Arbiters\\ReservedResources\\BrokenVideo "
+                "present in the registry? Restoring normal PCI ordering.\n",
+                Status);
+        ArbBuildAssignmentOrdering(CommonInstance,
+                                   L"Pci",
+                                   L"Pci",
+                                   PciArbTranslateOrdering);
+        return;
+    }
+
     /* Now the hack has been applied */
     FdoExtension->BrokenVideoHackApplied = TRUE;
 }

drivers/bus/pcix/debug.c

@@ -103,8 +103,10 @@ PciDebugPoIrpTypeToText(IN USHORT MinorFunction)
 {
     PCHAR Text;
 
-    /* Catch invalid code */
-    if (MinorFunction >= IRP_MN_QUERY_POWER)
+    /* Catch invalid code (QUERY_POWER is the highest code we decode, so only
+     * strictly-greater minor functions are unknown - the old ">=" mislabeled a
+     * perfectly valid IRP_MN_QUERY_POWER as "UNKNOWN PO IRP Minor Code") */
+    if (MinorFunction > IRP_MN_QUERY_POWER)
     {
         /* New version of Windows? Or driver bug */
         Text = "** UNKNOWN PO IRP Minor Code **";

drivers/bus/pcix/enum.c

@@ -68,6 +68,13 @@ PciComputeNewCurrentSettings(IN PPCI_PDO_EXTENSION PdoExtension,
     if (!ResourceList || !ResourceList->Count)
         return PdoExtension->UpdateHardware;
 
+    /* Fully zero the array: unmatched slots stay a CLEAN CmResourceTypeNull
+       (== 0) descriptor.  Without this the non-Type fields are uninitialized
+       stack memory, and the compare-and-update loop below copies that garbage
+       into Current[] via "*Old = *New" - which is what produced the bogus
+       "changed to: Type 0, ShareDisposition 0xAB, <pointer>" descriptors in the
+       bridge START dump. */
+    RtlZeroMemory(NewResources, sizeof(NewResources));
     for (i = 0; i < PCI_MAX_RANGE_COUNT; i++)
     {
         NewResources[i].Type = CmResourceTypeNull;
@@ -366,8 +373,12 @@ PciQueryResources(IN PPCI_PDO_EXTENSION PdoExtension,
         /* Are the memory decodes enabled? */
         if (HaveMemSpace)
         {
-            /* Build a memory descriptor for a 128KB framebuffer at 0xA0000 */
-            Resource->Flags = CM_RESOURCE_MEMORY_READ_WRITE;
+            /* Build a memory descriptor for a 128KB framebuffer at 0xA0000.
+               This range is forwarded to the VGA device behind the bridge, so
+               flag it as a forwarding window (CM_RESOURCE_MEMORY_WINDOW_DECODE)
+               and the child's identical decode will not be seen as a conflict. */
+            Resource->Flags = CM_RESOURCE_MEMORY_READ_WRITE |
+                              CM_RESOURCE_MEMORY_WINDOW_DECODE;
             Resource->u.Generic.Start.HighPart = 0;
             Resource->Type = CmResourceTypeMemory;
             Resource->u.Generic.Start.LowPart = 0xA0000;
@@ -378,16 +389,23 @@ PciQueryResources(IN PPCI_PDO_EXTENSION PdoExtension,
         /* Are the I/O decodes enabled? */
         if (HaveIoSpace)
         {
-            /* Build an I/O descriptor for the graphic ports at 0x3B0 */
+            /* Build an I/O descriptor for the graphic ports at 0x3B0.  These
+               legacy VGA ports are forwarded to the child VGA device, so they
+               are tagged as a forwarding window (CM_RESOURCE_PORT_WINDOW_DECODE)
+               to avoid a false conflict with the child's own VGA decode. */
             Resource->Type = CmResourceTypePort;
-            Resource->Flags = CM_RESOURCE_PORT_POSITIVE_DECODE | CM_RESOURCE_PORT_10_BIT_DECODE;
+            Resource->Flags = CM_RESOURCE_PORT_POSITIVE_DECODE |
+                              CM_RESOURCE_PORT_10_BIT_DECODE |
+                              CM_RESOURCE_PORT_WINDOW_DECODE;
             Resource->u.Port.Start.QuadPart = 0x3B0u;
             Resource->u.Port.Length = 0xC;
             Resource++;
 
             /* Build an I/O descriptor for the graphic ports at 0x3C0 */
             Resource->Type = CmResourceTypePort;
-            Resource->Flags = CM_RESOURCE_PORT_POSITIVE_DECODE | CM_RESOURCE_PORT_10_BIT_DECODE;
+            Resource->Flags = CM_RESOURCE_PORT_POSITIVE_DECODE |
+                              CM_RESOURCE_PORT_10_BIT_DECODE |
+                              CM_RESOURCE_PORT_WINDOW_DECODE;
             Resource->u.Port.Start.QuadPart = 0x3C0u;
             Resource->u.Port.Length = 0x20;
             Resource++;

drivers/bus/pcix/hookhal.c

@@ -25,15 +25,37 @@ NTAPI
 PciTranslateBusAddress(IN INTERFACE_TYPE InterfaceType,
                        IN ULONG BusNumber,
                        IN PHYSICAL_ADDRESS BusAddress,
-                       OUT PULONG AddressSpace,
+                       IN OUT PULONG AddressSpace,
                        OUT PPHYSICAL_ADDRESS TranslatedAddress)
 {
-    UNREFERENCED_PARAMETER(InterfaceType);
-    UNREFERENCED_PARAMETER(BusNumber);
-    UNREFERENCED_PARAMETER(AddressSpace);
+    /*
+     * This routine is hooked over the HAL's HalPciTranslateBusAddress (see
+     * PciHookHal), with the original HAL routine stashed in
+     * PcipSavedTranslateBusAddress.  Like the real pci.sys, the hook itself
+     * performs no translation arithmetic - it simply defers to the HAL, which
+     * owns the platform-specific PCI bus-address-to-physical mapping and the
+     * bus-handler chain (range/offset lookup, I/O vs. memory space, etc.).
+     * This is recursion-safe: the saved routine (HaliTranslateBusAddress)
+     * dispatches straight to a bus handler's TranslateBusAddress, never back
+     * through HalPciTranslateBusAddress.
+     */
+    if (PcipSavedTranslateBusAddress &&
+        PcipSavedTranslateBusAddress(InterfaceType,
+                                     BusNumber,
+                                     BusAddress,
+                                     AddressSpace,
+                                     TranslatedAddress))
+    {
+        return TRUE;
+    }
 
-    /* FIXME: Broken translation */
-    UNIMPLEMENTED;
+    /*
+     * Fallback for when the HAL has no registered translator for this PCI bus
+     * (common during this bring-up, where the new bus driver owns enumeration
+     * and the legacy HAL PCI bus handler may be absent).  On x86 a PCI bus
+     * address is identity-mapped to the CPU physical address for both memory
+     * and I/O space, so pass it through unchanged and leave AddressSpace as-is.
+     */
     TranslatedAddress->QuadPart = BusAddress.QuadPart;
     return TRUE;
 }

drivers/bus/pcix/intrface/cardbus.c

@@ -30,36 +30,97 @@ PCI_INTERFACE PciCardbusPrivateInterface =
 
 /* FUNCTIONS ******************************************************************/
 
+/*
+ * CardBus (PCI header type 2) resource configurator.
+ *
+ * The only PCI-arbitrated resource of a CardBus bridge is its socket (ExCA)
+ * registers BAR at offset 0x10. The four card-side memory/I/O decode windows
+ * (the type2 Range[] registers) are read/write registers programmed by the
+ * CardBus controller driver, not sizeable BARs, so they are not treated as
+ * device BARs here.
+ */
+
 VOID
 NTAPI
-Cardbus_SaveCurrentSettings(IN PPCI_CONFIGURATOR_CONTEXT Context)
+Cardbus_MassageHeaderForLimitsDetermination(IN PPCI_CONFIGURATOR_CONTEXT Context)
 {
-    UNREFERENCED_PARAMETER(Context);
-    UNIMPLEMENTED_DBGBREAK();
+    PPCI_COMMON_HEADER PciData, Current;
+
+    PciData = Context->PciData;
+    Current = Context->Current;
+
+    /* Write all 1s to the socket-registers BAR; the read-back shows which bits
+       are hardwired to 0, which gives the BAR length. */
+    PciData->u.type2.SocketRegistersBaseAddress = 0xFFFFFFFF;
+
+    /* Preserve the bus-number and latency fields across the discovery write */
+    PciData->u.type2.PrimaryBus = Current->u.type2.PrimaryBus;
+    PciData->u.type2.SecondaryBus = Current->u.type2.SecondaryBus;
+    PciData->u.type2.SubordinateBus = Current->u.type2.SubordinateBus;
+    PciData->u.type2.SecondaryLatency = Current->u.type2.SecondaryLatency;
+
+    /* The card decode windows (Range[]) are not sizeable BARs; leave them at
+       their current values so they are written back unchanged. */
+
+    /* Save and clear the write-1-to-clear secondary status register */
+    Context->SecondaryStatus = Current->u.type2.SecondaryStatus;
+    Current->u.type2.SecondaryStatus = 0;
+    PciData->u.type2.SecondaryStatus = 0;
 }
 
 VOID
 NTAPI
 Cardbus_SaveLimits(IN PPCI_CONFIGURATOR_CONTEXT Context)
 {
-    UNREFERENCED_PARAMETER(Context);
-    UNIMPLEMENTED_DBGBREAK();
+    PPCI_COMMON_HEADER PciData;
+    PPCI_FUNCTION_RESOURCES Resources;
+
+    /* PciData holds the sized BAR mask read back after the all-1s write */
+    PciData = Context->PciData;
+    Resources = Context->PdoExtension->Resources;
+
+    /* Build the limit descriptor for the socket-registers memory BAR. The
+       remaining limit descriptors are left NULL (the caller zeroed them). */
+    PciCreateIoDescriptorFromBarLimit(&Resources->Limit[0],
+                                      &PciData->u.type2.SocketRegistersBaseAddress,
+                                      FALSE);
 }
 
 VOID
 NTAPI
-Cardbus_MassageHeaderForLimitsDetermination(IN PPCI_CONFIGURATOR_CONTEXT Context)
+Cardbus_SaveCurrentSettings(IN PPCI_CONFIGURATOR_CONTEXT Context)
 {
-    UNREFERENCED_PARAMETER(Context);
-    UNIMPLEMENTED_DBGBREAK();
+    PPCI_COMMON_HEADER Current;
+    PPCI_FUNCTION_RESOURCES Resources;
+    PCM_PARTIAL_RESOURCE_DESCRIPTOR CmDescriptor;
+    PIO_RESOURCE_DESCRIPTOR IoDescriptor;
+
+    Current = Context->Current;
+    Resources = Context->PdoExtension->Resources;
+
+    /* Mirror the socket BAR's limit descriptor into a current-setting one,
+       using the live (programmed) base address. */
+    CmDescriptor = &Resources->Current[0];
+    IoDescriptor = &Resources->Limit[0];
+
+    CmDescriptor->Type = IoDescriptor->Type;
+    if (CmDescriptor->Type != CmResourceTypeNull)
+    {
+        CmDescriptor->Flags = IoDescriptor->Flags;
+        CmDescriptor->ShareDisposition = IoDescriptor->ShareDisposition;
+        CmDescriptor->u.Generic.Start.HighPart = 0;
+        CmDescriptor->u.Generic.Length = IoDescriptor->u.Generic.Length;
+        CmDescriptor->u.Memory.Start.LowPart =
+            Current->u.type2.SocketRegistersBaseAddress & PCI_ADDRESS_MEMORY_ADDRESS_MASK;
+    }
 }
 
 VOID
 NTAPI
 Cardbus_RestoreCurrent(IN PPCI_CONFIGURATOR_CONTEXT Context)
 {
-    UNREFERENCED_PARAMETER(Context);
-    UNIMPLEMENTED_DBGBREAK();
+    /* Restore the secondary status register saved during massaging */
+    Context->Current->u.type2.SecondaryStatus = Context->SecondaryStatus;
 }
 
 VOID
@@ -71,7 +132,9 @@ Cardbus_GetAdditionalResourceDescriptors(IN PPCI_CONFIGURATOR_CONTEXT Context,
     UNREFERENCED_PARAMETER(Context);
     UNREFERENCED_PARAMETER(PciData);
     UNREFERENCED_PARAMETER(IoDescriptor);
-    UNIMPLEMENTED_DBGBREAK();
+
+    /* A CardBus bridge exposes no additional fixed legacy resources here; the
+       card-side windows are owned by the CardBus controller driver. */
 }
 
 VOID
@@ -81,7 +144,8 @@ Cardbus_ResetDevice(IN PPCI_PDO_EXTENSION PdoExtension,
 {
     UNREFERENCED_PARAMETER(PdoExtension);
     UNREFERENCED_PARAMETER(PciData);
-    UNIMPLEMENTED_DBGBREAK();
+
+    /* No special reset handling required for a CardBus bridge. */
 }
 
 VOID
@@ -91,7 +155,12 @@ Cardbus_ChangeResourceSettings(IN PPCI_PDO_EXTENSION PdoExtension,
 {
     UNREFERENCED_PARAMETER(PdoExtension);
     UNREFERENCED_PARAMETER(PciData);
-    UNIMPLEMENTED_DBGBREAK();
+
+    /*
+     * PciData already holds the bridge's live configuration (read by
+     * PciSetResources). The socket BAR and the card decode windows keep their
+     * firmware-programmed values, so there is nothing to reprogram here.
+     */
 }
 
 NTSTATUS
@@ -119,9 +188,7 @@ pcicbintrf_Constructor(IN PVOID DeviceExtension,
     UNREFERENCED_PARAMETER(Version);
     UNREFERENCED_PARAMETER(Size);
     UNREFERENCED_PARAMETER(Interface);
-
-    /* Not yet implemented */
-    UNIMPLEMENTED_DBGBREAK();
+    DPRINT1("PCI pcicbintrf_Constructor, unexpected call.\n");
     return STATUS_NOT_IMPLEMENTED;
 }