Skip to content

Commit 74d4ef1

Browse files
mkopecSergiiDmytruk
mkopec
authored and
SergiiDmytruk
committed
vc/intel/fsp/fsp2_0/iot/meteorlake: add missing MemInfoHob from client vc dir
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
1 parent 5c53f82 commit 74d4ef1

1 file changed

Lines changed: 325 additions & 0 deletions

File tree

‎src/vendorcode/intel/fsp/fsp2_0/iot/meteorlake/MemInfoHob.h‎

Lines changed: 325 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,325 @@
1+
/** @file
2+
This file contains definitions required for creation of
3+
Memory S3 Save data, Memory Info data and Memory Platform
4+
data hobs.
5+
6+
@copyright
7+
Copyright (c) 1999 - 2022, Intel Corporation. All rights reserved.<BR>
8+
This program and the accompanying materials are licensed and made available under
9+
the terms and conditions of the BSD License that accompanies this distribution.
10+
The full text of the license may be found at
11+
http://opensource.org/licenses/bsd-license.php.
12+
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13+
14+
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15+
16+
@par Specification Reference:
17+
**/
18+
#ifndef _MEM_INFO_HOB_H_
19+
#define _MEM_INFO_HOB_H_
20+
21+
22+
#pragma pack (push, 1)
23+
24+
extern EFI_GUID gSiMemoryS3DataGuid;
25+
extern EFI_GUID gSiMemoryS3Data2Guid;
26+
extern EFI_GUID gSiMemoryInfoDataGuid;
27+
extern EFI_GUID gSiMemoryPlatformDataGuid;
28+
29+
#define MAX_NODE 2
30+
#define MAX_CH 4
31+
#define MAX_DDR5_CH 2
32+
#define MAX_DIMM 2
33+
// Must match definitions in
34+
// Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h
35+
#define HOB_MAX_SAGV_POINTS 4
36+
37+
///
38+
/// Host reset states from MRC.
39+
///
40+
#define WARM_BOOT 2
41+
42+
#define R_MC_CHNL_RANK_PRESENT 0x7C
43+
#define B_RANK0_PRS BIT0
44+
#define B_RANK1_PRS BIT1
45+
#define B_RANK2_PRS BIT4
46+
#define B_RANK3_PRS BIT5
47+
48+
// @todo remove and use the MdePkg\Include\Pi\PiHob.h
49+
#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
50+
#ifndef __HOB__H__
51+
typedef struct _EFI_HOB_GENERIC_HEADER {
52+
UINT16 HobType;
53+
UINT16 HobLength;
54+
UINT32 Reserved;
55+
} EFI_HOB_GENERIC_HEADER;
56+
57+
typedef struct _EFI_HOB_GUID_TYPE {
58+
EFI_HOB_GENERIC_HEADER Header;
59+
EFI_GUID Name;
60+
///
61+
/// Guid specific data goes here
62+
///
63+
} EFI_HOB_GUID_TYPE;
64+
#endif
65+
#endif
66+
67+
///
68+
/// Defines taken from MRC so avoid having to include MrcInterface.h
69+
///
70+
71+
//
72+
// Matches MAX_SPD_SAVE define in MRC
73+
//
74+
#ifndef MAX_SPD_SAVE
75+
#define MAX_SPD_SAVE 29
76+
#endif
77+
78+
//
79+
// MRC version description.
80+
//
81+
typedef struct {
82+
UINT8 Major; ///< Major version number
83+
UINT8 Minor; ///< Minor version number
84+
UINT8 Rev; ///< Revision number
85+
UINT8 Build; ///< Build number
86+
} SiMrcVersion;
87+
88+
//
89+
// Matches MrcChannelSts enum in MRC
90+
//
91+
#ifndef CHANNEL_NOT_PRESENT
92+
#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
93+
#endif
94+
#ifndef CHANNEL_DISABLED
95+
#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
96+
#endif
97+
#ifndef CHANNEL_PRESENT
98+
#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
99+
#endif
100+
101+
//
102+
// Matches MrcDimmSts enum in MRC
103+
//
104+
#ifndef DIMM_ENABLED
105+
#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
106+
#endif
107+
#ifndef DIMM_DISABLED
108+
#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
109+
#endif
110+
#ifndef DIMM_PRESENT
111+
#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
112+
#endif
113+
#ifndef DIMM_NOT_PRESENT
114+
#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
115+
#endif
116+
117+
//
118+
// Matches MrcBootMode enum in MRC
119+
//
120+
#ifndef __MRC_BOOT_MODE__
121+
#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
122+
#ifndef INT32_MAX
123+
#define INT32_MAX (0x7FFFFFFF)
124+
#endif //INT32_MAX
125+
typedef enum {
126+
bmCold, ///< Cold boot
127+
bmWarm, ///< Warm boot
128+
bmS3, ///< S3 resume
129+
bmFast, ///< Fast boot
130+
MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
131+
MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
132+
} MRC_BOOT_MODE;
133+
#endif //__MRC_BOOT_MODE__
134+
135+
//
136+
// Matches MrcDdrType enum in MRC
137+
//
138+
#ifndef MRC_DDR_TYPE_DDR5
139+
#define MRC_DDR_TYPE_DDR5 1
140+
#endif
141+
#ifndef MRC_DDR_TYPE_LPDDR5
142+
#define MRC_DDR_TYPE_LPDDR5 2
143+
#endif
144+
#ifndef MRC_DDR_TYPE_LPDDR4
145+
#define MRC_DDR_TYPE_LPDDR4 3
146+
#endif
147+
#ifndef MRC_DDR_TYPE_UNKNOWN
148+
#define MRC_DDR_TYPE_UNKNOWN 4
149+
#endif
150+
151+
#define MAX_PROFILE_NUM 7 // number of memory profiles supported
152+
#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported
153+
154+
#ifndef MAX_RCOMP_TARGETS
155+
#define MAX_RCOMP_TARGETS 5
156+
#endif
157+
158+
#ifndef MAX_ODT_ENTRIES
159+
#define MAX_ODT_ENTRIES 11
160+
#endif
161+
162+
#define MAX_TRACE_REGION 5
163+
#define MAX_TRACE_CACHE_TYPE 2
164+
165+
//
166+
// DIMM timings
167+
//
168+
typedef struct {
169+
UINT32 tCK; ///< Memory cycle time, in femtoseconds.
170+
UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
171+
UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
172+
UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
173+
UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
174+
UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
175+
UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
176+
UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
177+
UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
178+
UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
179+
UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
180+
UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
181+
UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
182+
UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
183+
UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
184+
UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
185+
UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
186+
UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
187+
UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
188+
UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
189+
UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
190+
UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
191+
UINT16 tCCD_L_WR; ///< Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank group.
192+
} MRC_CH_TIMING;
193+
194+
typedef struct {
195+
UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay
196+
} MRC_IP_TIMING;
197+
198+
///
199+
/// Memory SMBIOS & OC Memory Data Hob
200+
///
201+
typedef struct {
202+
UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
203+
UINT8 DimmId;
204+
UINT32 DimmCapacity; ///< DIMM size in MBytes.
205+
UINT16 MfgId;
206+
UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DDR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
207+
UINT8 RankInDimm; ///< The number of ranks in this DIMM.
208+
UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
209+
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
210+
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
211+
UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
212+
UINT16 Speed; ///< The maximum capable speed of the device, in MHz
213+
UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
214+
} DIMM_INFO;
215+
216+
typedef struct {
217+
UINT8 Status; ///< Indicates whether this channel should be used.
218+
UINT8 ChannelId;
219+
UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
220+
MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
221+
DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
222+
} CHANNEL_INFO;
223+
224+
typedef struct {
225+
UINT8 Status; ///< Indicates whether this controller should be used.
226+
UINT16 DeviceId; ///< The PCI device id of this memory controller.
227+
UINT8 RevisionId; ///< The PCI revision id of this memory controller.
228+
UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
229+
CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
230+
} CONTROLLER_INFO;
231+
232+
typedef struct {
233+
UINT64 BaseAddress; ///< Trace Base Address
234+
UINT64 TotalSize; ///< Total Trace Region of Same Cache type
235+
UINT8 CacheType; ///< Trace Cache Type
236+
UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
237+
UINT8 Rsvd[2];
238+
} PSMI_MEM_INFO;
239+
240+
/// This data structure contains per-SaGv timing values that are considered output by the MRC.
241+
typedef struct {
242+
UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s
243+
MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec
244+
MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific
245+
} HOB_SAGV_TIMING_OUT;
246+
247+
/// This data structure contains SAGV config values that are considered output by the MRC.
248+
typedef struct {
249+
UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled.
250+
UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point.
251+
HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS];
252+
} HOB_SAGV_INFO;
253+
254+
typedef struct {
255+
UINT8 Revision;
256+
UINT16 DataWidth; ///< Data width, in bits, of this memory device
257+
/** As defined in SMBIOS 3.0 spec
258+
Section 7.18.2 and Table 75
259+
**/
260+
UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
261+
UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
262+
UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
263+
/** As defined in SMBIOS 3.0 spec
264+
Section 7.17.3 and Table 72
265+
**/
266+
UINT8 ErrorCorrectionType;
267+
268+
SiMrcVersion Version;
269+
BOOLEAN EccSupport;
270+
UINT8 MemoryProfile;
271+
UINT32 TotalPhysicalMemorySize;
272+
UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
273+
UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
274+
UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed
275+
BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.
276+
UINT16 Ratio; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255
277+
UINT8 RefClk;
278+
UINT32 VddVoltage[MAX_PROFILE_NUM];
279+
UINT32 VddqVoltage[MAX_PROFILE_NUM];
280+
UINT32 VppVoltage[MAX_PROFILE_NUM];
281+
UINT16 RcompTarget[MAX_PROFILE_NUM][MAX_RCOMP_TARGETS];
282+
UINT16 DimmOdt[MAX_PROFILE_NUM][MAX_DIMM][MAX_ODT_ENTRIES];
283+
CONTROLLER_INFO Controller[MAX_NODE];
284+
UINT32 NumPopulatedChannels; ///< Total number of memory channels populated
285+
HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC.
286+
BOOLEAN IsIbeccEnabled;
287+
UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels
288+
UINT16 PprDetectedErrors; ///< PPR: Counts of detected bad rows
289+
UINT16 PprRepairFails; ///< PPR: Counts of repair failure
290+
UINT16 PprForceRepairStatus; ///< PPR: Force Repair Status
291+
} MEMORY_INFO_DATA_HOB;
292+
293+
/**
294+
Memory Platform Data Hob
295+
296+
<b>Revision 1:</b>
297+
- Initial version.
298+
<b>Revision 2:</b>
299+
- Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
300+
**/
301+
typedef struct {
302+
UINT8 Revision;
303+
UINT8 Reserved[3];
304+
UINT32 BootMode;
305+
UINT32 TsegSize;
306+
UINT32 TsegBase;
307+
UINT32 PrmrrSize;
308+
UINT64 PrmrrBase;
309+
UINT32 GttBase;
310+
UINT32 MmioSize;
311+
UINT32 PciEBaseAddress;
312+
PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
313+
PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION];
314+
BOOLEAN MrcBasicMemoryTestPass;
315+
} MEMORY_PLATFORM_DATA;
316+
317+
typedef struct {
318+
EFI_HOB_GUID_TYPE EfiHobGuidType;
319+
MEMORY_PLATFORM_DATA Data;
320+
UINT8 *Buffer;
321+
} MEMORY_PLATFORM_DATA_HOB;
322+
323+
#pragma pack (pop)
324+
325+
#endif // _MEM_INFO_HOB_H_

0 commit comments

Comments
 (0)