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mb/msi/ms7e56/devicetree.cb: Add USB controller configuration
Add USB controller tuning settings and OC pin map based on registers dumped from vendor BIOS. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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‎src/mainboard/msi/ms7e56/devicetree.cb‎

Lines changed: 154 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,160 @@ chip soc/amd/phoenix
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register "pspp_policy" = "DXIO_PSPP_DISABLED"
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register "usb_phy_custom" = "true"
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register "usb_phy" = "{
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.Usb2PhyPort[0] = {
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.compdistune = 0x1,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xc,
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.sqrxtune = 0x2,
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.txfslstune = 0x1,
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.txpreempamptune = 0x3,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb2PhyPort[1] = {
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.compdistune = 0x1,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xc,
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.sqrxtune = 0x2,
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.txfslstune = 0x1,
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.txpreempamptune = 0x3,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb2PhyPort[2] = {
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.compdistune = 0x1,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xc,
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.sqrxtune = 0x2,
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.txfslstune = 0x1,
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.txpreempamptune = 0x3,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb2PhyPort[3] = {
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.compdistune = 0x1,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xc,
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.sqrxtune = 0x2,
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.txfslstune = 0x1,
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.txpreempamptune = 0x3,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb2PhyPort[4] = {
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.compdistune = 0x1,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xc,
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.sqrxtune = 0x2,
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.txfslstune = 0x1,
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.txpreempamptune = 0x3,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb2PhyPort[5] = {
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.compdistune = 0x1,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xc,
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.sqrxtune = 0x2,
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.txfslstune = 0x1,
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.txpreempamptune = 0x3,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb2PhyPort[6] = {
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.compdistune = 0x1,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xc,
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.sqrxtune = 0x2,
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.txfslstune = 0x1,
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.txpreempamptune = 0x3,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb2PhyPort[7] = {
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.compdistune = 0x1,
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.pllbtune = 0x1,
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.pllitune = 0x0,
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.pllptune = 0xc,
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.sqrxtune = 0x2,
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.txfslstune = 0x1,
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.txpreempamptune = 0x3,
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.txpreemppulsetune = 0x0,
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.txrisetune = 0x1,
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.txvreftune = 0x3,
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.txhsxvtune = 0x3,
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.txrestune = 0x2,
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},
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.Usb3PhyPort[0] = {
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.tx_term_ctrl = 0x2,
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.rx_term_ctrl = 0x2,
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.tx_vboost_lvl_en = 0x0,
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.tx_vboost_lvl = 0x5,
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},
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.Usb3PhyPort[1] = {
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.tx_term_ctrl = 0x2,
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.rx_term_ctrl = 0x2,
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.tx_vboost_lvl_en = 0x0,
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.tx_vboost_lvl = 0x5,
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},
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.Usb3PhyPort[2] = {
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.tx_term_ctrl = 0x2,
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.rx_term_ctrl = 0x2,
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.tx_vboost_lvl_en = 0x0,
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.tx_vboost_lvl = 0x5,
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},
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.ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_ONLY,
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.ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_ONLY,
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.ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_ONLY,
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}"
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register "usb3_force_gen1" = "{
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.port0 = 1,
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.port2 = 1,
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}"
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register "polarity_cfg_low" = "true"
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register "usb2_oc_pins[0]" = "{ 0x2, 0x3, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
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register "usb2_oc_pins[1]" = "{ 0x3, 0x3, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
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register "usb2_oc_pins[2]" = "{ 0x1, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
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register "usb2_oc_pins[3]" = "{ 0x1, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
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register "usb3_oc_pins[0]" = "{ 0x2, 0x3, 0xf, 0xf }"
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register "usb3_oc_pins[1]" = "{ 0x3, 0xf, 0xf, 0xf }"
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register "usb3_oc_pins[2]" = "{ 0x1, 0xf, 0xf, 0xf }"
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register "usb3_oc_pins[3]" = "{ 0x1, 0xf, 0xf, 0xf }"
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device domain 0 on
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device ref iommu on end
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