mb/emulation/qemu-q35: get rid of CONFIG_UNKNOWN_TSC_RATE

This option signifies missing implementation of tsc_freq_mhz() which
results in tsc_freq_mhz() from src/arch/x86/timestamp.c returning zero.
That zero in turn gets put into TIMESTAMP CBMEM table requiring payloads
and user-space tools to figure the frequency on their own.

Implement tsc_freq_mhz() to query timer frequency in coreboot, so it
gets reported downstream.

Change-Id: I88d1206c13f15a9f20c07b65dcec42ec614f7e6a
Upstream-Status: Pending
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>

Author: SergiiDmytruk

src/cpu/qemu-x86/Kconfig

@@ -6,7 +6,6 @@ config CPU_QEMU_X86
 	select HAVE_X86_64_SUPPORT
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER
-	select UNKNOWN_TSC_RATE
 	select NEED_SMALL_2MB_PAGE_TABLES	# QEMU doesn't support 1GB pages
 	select IDT_IN_EVERY_STAGE
 

src/mainboard/emulation/qemu-q35/Makefile.mk

@@ -1,11 +1,14 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 bootblock-y += bootblock.c
+bootblock-y += timer.c
 
 romstage-y += ../qemu-i440fx/memmap.c
+romstage-y += timer.c
 
 postcar-y += ../qemu-i440fx/memmap.c
 postcar-y += ../qemu-i440fx/exit_car.S
+postcar-y += timer.c
 
 ramstage-y += ../qemu-i440fx/memmap.c
 ramstage-y += ../qemu-i440fx/northbridge.c

src/mainboard/emulation/qemu-q35/timer.c

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <cpu/x86/tsc.h>
+#include <device/pci_ops.h>
+#include <southbridge/intel/common/pmutil.h>
+
+unsigned long tsc_freq_mhz(void)
+{
+	/* Mimics implementation of acpi_fill_fadt() in southbridge/intel/i82801ix/fadt.c. */
+	u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffe;
+	u16 pm_tmr_blk = pmbase + PM1_TMR;
+	return inl(pm_tmr_blk);
+}