From b3aa30411cfbe114d7da2e879b8b160b6b10f438 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Filip=20Lewi=C5=84ski?= Date: Tue, 22 Jul 2025 11:43:17 +0200 Subject: [PATCH 1/6] mb/novacustom/nuc_box/Kconfig: set MAINBOARD_FAMILY MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sets the MAINBOARD_FAMILY SMBIOS option to Not Applicable, to match what the stock firmware does. Upstream-Status: Pending Signed-off-by: Filip Lewiński --- src/mainboard/novacustom/nuc_box/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/novacustom/nuc_box/Kconfig b/src/mainboard/novacustom/nuc_box/Kconfig index 7f590919c50..83b63e8cbb9 100644 --- a/src/mainboard/novacustom/nuc_box/Kconfig +++ b/src/mainboard/novacustom/nuc_box/Kconfig @@ -46,6 +46,10 @@ config MAINBOARD_SMBIOS_PRODUCT_NAME config MAINBOARD_VERSION default "nuc_box" if BOARD_NOVACUSTOM_NUC_BOX +config MAINBOARD_FAMILY + string + default "Not Applicable" # Match Insyde firmware + config CMOS_DEFAULT_FILE default "src/mainboard/\$(MAINBOARDDIR)/cmos.default" From 7bab25565365e099aacd8c64b3aa358397dc9083 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Filip=20Lewi=C5=84ski?= Date: Tue, 22 Jul 2025 11:47:20 +0200 Subject: [PATCH 2/6] configs/config.novacustom_nuc_box: update to resolve regression issues MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Changes: - Enable SMM BWP - supported thanks to recent SMMSTORE fixes - Show WiFi/BT enable option - for feature parity - Disable console redirection to nonexistent serial port - speeds up booting significantly - Increase CBMEM buffer size Upstream-Status: Inappropriate [Dasharo downstream] Signed-off-by: Filip Lewiński --- configs/config.novacustom_nuc_box | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configs/config.novacustom_nuc_box b/configs/config.novacustom_nuc_box index ac9ae086337..2a021ab36e1 100644 --- a/configs/config.novacustom_nuc_box +++ b/configs/config.novacustom_nuc_box @@ -2,11 +2,13 @@ CONFIG_LOCALVERSION="v0.9.0-rc3" CONFIG_OPTION_BACKEND_NONE=y CONFIG_VENDOR_NOVACUSTOM=y CONFIG_MAINBOARD_VENDOR="NovaCustom" +# CONFIG_CONSOLE_SERIAL is not set # CONFIG_POST_IO is not set CONFIG_VBOOT=y CONFIG_VBOOT_SLOTS_RW_A=y CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/novacustom/nuc_box/ifd.bin" CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/novacustom/nuc_box/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x200000 CONFIG_HAVE_IFD_BIN=y CONFIG_BOARD_NOVACUSTOM_NUC_BOX=y CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/novacustom/bootsplash.bmp" @@ -26,6 +28,8 @@ CONFIG_ADD_FSP_BINARIES=y CONFIG_FSP_FULL_FD=y CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y CONFIG_PAYLOAD_EDK2=y CONFIG_EDK2_USE_EDK2_PLATFORMS=y CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" @@ -47,6 +51,7 @@ CONFIG_EDK2_SETUP_PASSWORD=y CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y CONFIG_EDK2_DASHARO_USB_CONFIG=y CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y From ee072a639908211013da9ea1e6725e35e1188150 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Filip=20Lewi=C5=84ski?= Date: Tue, 22 Jul 2025 14:28:42 +0200 Subject: [PATCH 3/6] mb/novacustom/nuc_box/ramstage.c: enable S3 sleep MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set the s0ix_enable parameter in accordance with chosen sleep mode. Upstream-Status: Pending Signed-off-by: Filip Lewiński --- src/mainboard/novacustom/nuc_box/ramstage.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/novacustom/nuc_box/ramstage.c b/src/mainboard/novacustom/nuc_box/ramstage.c index 46f121ad8e8..b83d622455a 100644 --- a/src/mainboard/novacustom/nuc_box/ramstage.c +++ b/src/mainboard/novacustom/nuc_box/ramstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -11,6 +12,14 @@ static void mainboard_init(void *chip_info) do_smbus_write_byte(CONFIG_FIXED_SMBUS_IO_BASE, 0xBA >> 1, 0x0F, 0xAA); } +void mainboard_update_soc_chip_config(struct soc_intel_meteorlake_config *config) +{ + if (get_sleep_type_option() == SLEEP_TYPE_OPTION_S3) + config->s0ix_enable = 0; + else + config->s0ix_enable = 1; +} + struct chip_operations mainboard_ops = { .init = mainboard_init, }; From b558f8ae0425c935ecf6fc5d5328b7b0cf768cd2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Filip=20Lewi=C5=84ski?= Date: Thu, 24 Jul 2025 11:57:07 +0200 Subject: [PATCH 4/6] mb/novacustom/nuc_box/variants/nuc_box/data.vbt: update MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The VBT extracted from debugfs of a running system didn't work with the FSP graphics init. Now with the appropriate version of a manually configured VBT the FSP GFX init works and the EDK2 GOP driver is no longer necessary. Upstream-Status: Pending Signed-off-by: Filip Lewiński --- configs/config.novacustom_nuc_box | 2 -- .../nuc_box/variants/nuc_box/data.vbt | Bin 7680 -> 7680 bytes 2 files changed, 2 deletions(-) diff --git a/configs/config.novacustom_nuc_box b/configs/config.novacustom_nuc_box index 2a021ab36e1..a73f4ee8906 100644 --- a/configs/config.novacustom_nuc_box +++ b/configs/config.novacustom_nuc_box @@ -17,7 +17,6 @@ CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/MeteorLakeFspBinPkg CONFIG_SOFTWARE_CONNECTION_MANAGER=y CONFIG_VALIDATE_INTEL_DESCRIPTOR=y CONFIG_HAVE_ME_BIN=y -CONFIG_NO_GFX_INIT=y CONFIG_DRIVERS_EFI_VARIABLE_STORE=y CONFIG_DRIVERS_EFI_FW_INFO=y CONFIG_DRIVERS_EFI_MAIN_FW_GUID="6f3f1f8c-f0a1-42d4-adee-14b476f9e066" @@ -38,7 +37,6 @@ CONFIG_EDK2_CBMEM_LOGGING=y CONFIG_EDK2_FOLLOW_BGRT_SPEC=y CONFIG_EDK2_SERIAL_SUPPORT=y CONFIG_EDK2_FTDI_USB_UART_SUPPORT=y -CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/novacustom/nuc_box/IntelGopDriver.efi" CONFIG_BUILD_IPXE=y CONFIG_IPXE_ADD_SCRIPT=y CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" diff --git a/src/mainboard/novacustom/nuc_box/variants/nuc_box/data.vbt b/src/mainboard/novacustom/nuc_box/variants/nuc_box/data.vbt index 93276b46fac7ede5838a977d7b096ba509227f02..64207eb3e2506246f8b0d6b51a678f344c985291 100644 GIT binary patch delta 325 zcmZp$X|S0f!5S#j%wRCNkWqM|fdDH5qZot2Mps8h_Nk0aEDQ`9lY1G}8UIb*!l+*V zkA>k<0)v16L!q<)0~9a<=>rT5j0zwI6#R35s_TWS1IjT0q%q8KWGh1C-Z1nU6_g@;^qlBn5_J86f%j(gF-1zzZfBjxZ!JDlmfB%wPcl zsIuKqW&B`Kpt1rKWlSJpplR2k%7lR2$sZYoIl)E&B|cAH2eDX?0VD(z;g^9}%rLo+ yNo;Z&oBCu~W=-+a%qKubp@3*suE~+iwoIHUlMgW4PF~NfviUDFv(#h(W-b7XhAt!k From 121fc4f9955672c341ac678bd10246ee0d9fcac6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Filip=20Lewi=C5=84ski?= Date: Mon, 28 Jul 2025 13:11:39 +0200 Subject: [PATCH 5/6] mb/novacustom/nuc_box/devicetree.cb: devicetree fixes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set the p2sb to hidden, since that's the state FSP leaves it in. This resolves the "not found, hiding it" message in cbmem. Enable the IPU. Upstream-Status: Pending Signed-off-by: Filip Lewiński --- src/mainboard/novacustom/nuc_box/devicetree.cb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/novacustom/nuc_box/devicetree.cb b/src/mainboard/novacustom/nuc_box/devicetree.cb index 4f0e2c13e64..8426163eebf 100644 --- a/src/mainboard/novacustom/nuc_box/devicetree.cb +++ b/src/mainboard/novacustom/nuc_box/devicetree.cb @@ -44,7 +44,7 @@ chip soc/intel/meteorlake register "pmc_gpe0_dw1" = "PMC_GPP_E" register "pmc_gpe0_dw2" = "PMC_GPP_H" end - device ref p2sb on end + device ref p2sb hidden end device ref hda on register "pch_hda_sdi_enable[0]" = "1" register "pch_hda_audio_link_hda_enable" = "1" @@ -54,6 +54,7 @@ chip soc/intel/meteorlake end device ref smbus on end device ref fast_spi on end + device ref ipu on end end chip drivers/crb device mmio 0xfed40000 on end From 370a7dc58e86dc8bebdcc37e4794e2993d6d1281 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Filip=20Lewi=C5=84ski?= Date: Mon, 28 Jul 2025 16:13:52 +0200 Subject: [PATCH 6/6] arch/x86/smbios.c: fix incorrect L3 cache size in SMBIOS Type 7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit L3 cache is typically unified and shared across all logical CPUs. The CPUID leaf 0x4 already reports the total cache size for such shared caches. Multiplying L3 size by the number of cores sharing it results in an inflated value that may exceed SMBIOS limits or be misinterpreted, leading Windows and other OSes to report the L3 cache size as zero. Upstream-Status: Pending Signed-off-by: Filip Lewiński --- src/arch/x86/smbios.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index a35e9a229d4..db83e420a5c 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -240,7 +240,20 @@ int smbios_write_type7_cache_parameters(unsigned long *current, const u8 level = info.level; const size_t assoc = info.num_ways; const size_t cache_share = info.num_cores_shared; - const size_t cache_size = info.size * get_number_of_caches(cache_share); + + /* + * In the case of unified L3 cache, the info_size is already the correct + * total size. Multiplying by number of cores is unnecessary and might result + * in the cache displaying as zero. + */ + size_t tmp_cache_size; + if (level < 3) { + tmp_cache_size = info.size * get_number_of_caches(cache_share); + } + else { + tmp_cache_size = info.size; + } + const size_t cache_size = tmp_cache_size; if (!cache_type) /* No more caches in the system */