diff --git a/src/device/oprom/x86emu/debug.h b/src/device/oprom/x86emu/debug.h index 01f633cb5c1..809c773a436 100644 --- a/src/device/oprom/x86emu/debug.h +++ b/src/device/oprom/x86emu/debug.h @@ -40,6 +40,8 @@ #define __X86EMU_DEBUG_H #include +#include +#include /*---------------------- Macros and type definitions ----------------------*/ diff --git a/src/device/oprom/yabel/biosemu.c b/src/device/oprom/yabel/biosemu.c index d0586c27836..89f878da5ea 100644 --- a/src/device/oprom/yabel/biosemu.c +++ b/src/device/oprom/yabel/biosemu.c @@ -55,6 +55,7 @@ #if CONFIG(X86EMU_DEBUG_TIMINGS) #include struct mono_time zero; +struct mono_time now; #endif static X86EMU_memFuncs my_mem_funcs = { diff --git a/src/device/oprom/yabel/debug.h b/src/device/oprom/yabel/debug.h index 626b6c81593..da146f3af51 100644 --- a/src/device/oprom/yabel/debug.h +++ b/src/device/oprom/yabel/debug.h @@ -39,6 +39,7 @@ #if CONFIG(X86EMU_DEBUG_TIMINGS) extern struct mono_time zero; +extern struct mono_time now; #endif extern u32 debug_flags; // from x86emu...needed for debugging @@ -100,7 +101,7 @@ static inline void set_ci(void) {}; // to be executed, since the x86emu advances CS:IP _before_ actually executing an instruction #if CONFIG(X86EMU_DEBUG_TIMINGS) -#define DEBUG_PRINTF_CS_IP(_x...) DEBUG_PRINTF("[%08lx]%x:%x ", (current_time_from(&zero)).microseconds, M.x86.R_CS, M.x86.R_IP); DEBUG_PRINTF(_x); +#define DEBUG_PRINTF_CS_IP(_x...) timer_monotonic_get(&now); DEBUG_PRINTF("[%lld]%x:%x ", mono_time_diff_microseconds(&zero, &now), M.x86.R_CS, M.x86.R_IP); DEBUG_PRINTF(_x); #else #define DEBUG_PRINTF_CS_IP(_x...) DEBUG_PRINTF("%x:%x ", M.x86.R_CS, M.x86.R_IP); DEBUG_PRINTF(_x); #endif diff --git a/src/mainboard/msi/ms7e56/devicetree.cb b/src/mainboard/msi/ms7e56/devicetree.cb index 8c75ca87471..586b69f44e1 100644 --- a/src/mainboard/msi/ms7e56/devicetree.cb +++ b/src/mainboard/msi/ms7e56/devicetree.cb @@ -45,6 +45,160 @@ chip soc/amd/phoenix register "pspp_policy" = "DXIO_PSPP_DISABLED" + register "usb_phy_custom" = "true" + + register "usb_phy" = "{ + .Usb2PhyPort[0] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[1] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[2] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[3] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[4] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[5] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[6] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[7] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb3PhyPort[0] = { + .tx_term_ctrl = 0x2, + .rx_term_ctrl = 0x2, + .tx_vboost_lvl_en = 0x0, + .tx_vboost_lvl = 0x5, + }, + .Usb3PhyPort[1] = { + .tx_term_ctrl = 0x2, + .rx_term_ctrl = 0x2, + .tx_vboost_lvl_en = 0x0, + .tx_vboost_lvl = 0x5, + }, + .Usb3PhyPort[2] = { + .tx_term_ctrl = 0x2, + .rx_term_ctrl = 0x2, + .tx_vboost_lvl_en = 0x0, + .tx_vboost_lvl = 0x5, + }, + .ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_ONLY, + .ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_ONLY, + .ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_ONLY, + }" + + register "usb3_force_gen1" = "{ + .port0 = 1, + .port2 = 1, + }" + + register "polarity_cfg_low" = "true" + + register "usb2_oc_pins[0]" = "{ 0x2, 0x3, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }" + register "usb2_oc_pins[1]" = "{ 0x3, 0x3, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }" + register "usb2_oc_pins[2]" = "{ 0x1, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }" + register "usb2_oc_pins[3]" = "{ 0x1, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }" + register "usb3_oc_pins[0]" = "{ 0x2, 0x3, 0xf, 0xf }" + register "usb3_oc_pins[1]" = "{ 0x3, 0xf, 0xf, 0xf }" + register "usb3_oc_pins[2]" = "{ 0x1, 0xf, 0xf, 0xf }" + register "usb3_oc_pins[3]" = "{ 0x1, 0xf, 0xf, 0xf }" + device domain 0 on device ref iommu on end diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk index f454cbbfcfc..c63cc852be4 100644 --- a/src/soc/amd/phoenix/Makefile.mk +++ b/src/soc/amd/phoenix/Makefile.mk @@ -16,6 +16,9 @@ all_x86-y += gpio.c all_x86-y += i3c.c all_x86-y += uart.c +all_x86-y += lpc.c +smm-y += lpc.c + bootblock-y += early_fch.c bootblock-y += espi_util.c diff --git a/src/soc/amd/phoenix/chip.h b/src/soc/amd/phoenix/chip.h index fb0ef0f78a2..1fe18cd15b0 100644 --- a/src/soc/amd/phoenix/chip.h +++ b/src/soc/amd/phoenix/chip.h @@ -106,8 +106,56 @@ struct soc_amd_phoenix_config { } pspp_policy; bool usb_phy_custom; + struct usb_phy_config usb_phy; + /* + * XHCI0 has 5 USB2 ports + * XHCI1 has 1 USB2 port + * USB4 XHCI has 1 USB2 port each + */ + struct { + uint8_t port0 : 4; + uint8_t port1 : 4; + uint8_t port2 : 4; + uint8_t port3 : 4; + uint8_t port4 : 4; + uint8_t port5 : 4; + uint8_t port6 : 4; + uint8_t port7 : 4; + } usb2_oc_pins[4]; + /* + * XHCI0 has 2 USB3 ports + * XHCI1 has 1 USB3 port + * USB4 XHCI has 1 USB3 port each + */ + struct { + uint8_t port0 : 4; + uint8_t port1 : 4; + uint8_t port2 : 4; + uint8_t port3 : 4; + } usb3_oc_pins[4]; + + bool polarity_cfg_low; + + /* + * Force gen1 for XHCI. + * bits [1:0] for XHCI0 port 0-1 + * bit 2 for XHCI1 port 0 + * bit 3 for first USB4 XHCI port 0 + * bit 4 for second USB4 XHCI port 0 + */ + union { + struct { + uint8_t port0 : 1; + uint8_t port1 : 1; + uint8_t port2 : 1; + uint8_t port3 : 1; + uint8_t port4 : 1; + }; + uint8_t raw; + } usb3_force_gen1; + #if !CONFIG(PLATFORM_USES_FSP2_0) struct ddi_descriptor ddi[DDI_DESCRIPTOR_COUNT]; #endif diff --git a/src/soc/amd/phoenix/chip_opensil.h b/src/soc/amd/phoenix/chip_opensil.h index 37170ad453d..2dfe204674c 100644 --- a/src/soc/amd/phoenix/chip_opensil.h +++ b/src/soc/amd/phoenix/chip_opensil.h @@ -60,15 +60,6 @@ struct fch_usb3_phy { uint8_t tx_vboost_lvl; ///< TX_VBOOST_LVL }; -#define USB0_PORT0 0 -#define USB0_PORT1 1 -#define USB0_PORT2 1 -#define USB0_PORT3 3 -#define USB1_PORT0 (0<<2) -#define USB1_PORT1 (1<<2) -#define USB1_PORT2 (1<<2) -#define USB1_PORT3 (3<<2) - #define USB_COMBO_PHY_MODE_USB_C 0 #define USB_COMBO_PHY_MODE_USB_ONLY 1 #define USB_COMBO_PHY_MODE_USB_DPM 2 @@ -80,6 +71,7 @@ struct usb_phy_config { uint8_t BatteryChargerEnable; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] uint8_t PhyP3CpmP4Support; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] uint8_t ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP + uint8_t Usb4Phy[USBC_COMBO_PHY_COUNT]; /// bit[3:0]-USB4 Port0, bit[7:4]-USB4 Port1 }; #endif /* PHOENIX_CHIP_OPENSIL_H */ diff --git a/src/soc/amd/phoenix/chipset_opensil.cb b/src/soc/amd/phoenix/chipset_opensil.cb index 30ef06767e6..0a88128c480 100644 --- a/src/soc/amd/phoenix/chipset_opensil.cb +++ b/src/soc/amd/phoenix/chipset_opensil.cb @@ -1,4 +1,14 @@ chip soc/amd/phoenix + + register "usb2_oc_pins[0]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }" + register "usb2_oc_pins[1]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }" + register "usb2_oc_pins[2]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }" + register "usb2_oc_pins[3]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }" + register "usb3_oc_pins[0]" = "{ 0xf, 0xf, 0xf, 0xf }" + register "usb3_oc_pins[1]" = "{ 0xf, 0xf, 0xf, 0xf }" + register "usb3_oc_pins[2]" = "{ 0xf, 0xf, 0xf, 0xf }" + register "usb3_oc_pins[3]" = "{ 0xf, 0xf, 0xf, 0xf }" + device cpu_cluster 0 on ops amd_cpu_bus_ops end @@ -160,6 +170,9 @@ chip soc/amd/phoenix device pci 18.7 alias data_fabric_7 on ops amd_data_fabric_ops end end + device mmio 0xfec11000 alias hfp off end + device mmio 0xfec12000 alias hid_2 off end + device mmio 0xfec13000 alias hid off end device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end diff --git a/src/soc/amd/phoenix/fch.c b/src/soc/amd/phoenix/fch.c index d1b99f0eb67..df1dd8850d1 100644 --- a/src/soc/amd/phoenix/fch.c +++ b/src/soc/amd/phoenix/fch.c @@ -144,6 +144,7 @@ static void cgpll_clock_gate_init(void) misc_write32(MISC_CLKGATEDCNTL, t); t = misc_read32(MISC_CGPLL_CONFIGURATION0); + t |= USB_PHY_CMCLK_ZSTATE_DIS; t |= USB_PHY_CMCLK_S3_DIS; t |= USB_PHY_CMCLK_S0I3_DIS; t |= USB_PHY_CMCLK_S5_DIS; diff --git a/src/soc/amd/phoenix/include/soc/southbridge.h b/src/soc/amd/phoenix/include/soc/southbridge.h index db0e30440d4..60ac3951f9d 100644 --- a/src/soc/amd/phoenix/include/soc/southbridge.h +++ b/src/soc/amd/phoenix/include/soc/southbridge.h @@ -93,6 +93,7 @@ #define XTAL_PAD_S3_TURNOFF_EN BIT(20) #define XTAL_PAD_S5_TURNOFF_EN BIT(21) #define MISC_CGPLL_CONFIGURATION0 0x30 +#define USB_PHY_CMCLK_ZSTATE_DIS BIT(1) #define USB_PHY_CMCLK_S3_DIS BIT(8) #define USB_PHY_CMCLK_S0I3_DIS BIT(9) #define USB_PHY_CMCLK_S5_DIS BIT(10) diff --git a/src/soc/amd/phoenix/lpc.c b/src/soc/amd/phoenix/lpc.c new file mode 100644 index 00000000000..b49c22fc8b2 --- /dev/null +++ b/src/soc/amd/phoenix/lpc.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void soc_lpc_tpm_decode_spi(void) +{ + /* SoC-specific SPI TPM setting */ + spi_write32(SPI_CNTRL0, spi_read32(SPI_CNTRL0) | (1 << 13)); + spi_write32(SPI100_HOST_PREF_CONFIG, spi_read32(SPI100_HOST_PREF_CONFIG) | (1 << 25)); +} diff --git a/src/vendorcode/amd/opensil/phoenix_poc/opensil b/src/vendorcode/amd/opensil/phoenix_poc/opensil index f38b340b543..0f806f9815c 160000 --- a/src/vendorcode/amd/opensil/phoenix_poc/opensil +++ b/src/vendorcode/amd/opensil/phoenix_poc/opensil @@ -1 +1 @@ -Subproject commit f38b340b54325c9788afa3346c8640de7630de1b +Subproject commit 0f806f9815c5ed14d69acbc40202078af67964e8 diff --git a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c index 49599ee1aaa..7fdf5441dbb 100644 --- a/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c +++ b/src/vendorcode/amd/opensil/phoenix_poc/ramstage.c @@ -3,6 +3,8 @@ #include #include #include +#include +#include #include #include #include @@ -11,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -76,7 +79,13 @@ static void setup_rc_manager_default(SIL_CONTEXT *SilContext) rc_mgr_input_block->AmdSmee = true; } +#define TACOMA_USB_STRUCT_MAJOR_VERSION 0xf +#define TACOMA_USB_STRUCT_MINOR_VERSION 0x1 + +static FCH_TC_USB_OEM_PLATFORM_TABLE usb_config = { 0 }; + #define NUM_XHCI_CONTROLLERS 4 +#define NUM_USB4_CONTROLLERS 2 static void configure_usb(SIL_CONTEXT *SilContext) { struct device *usb_ctrlr[NUM_XHCI_CONTROLLERS] = { @@ -85,6 +94,53 @@ static void configure_usb(SIL_CONTEXT *SilContext) DEV_PTR(usb4_xhci_0), DEV_PTR(usb4_xhci_1) }; + + struct device *usb4_rt[NUM_USB4_CONTROLLERS] = { + DEV_PTR(usb4_router_0), + DEV_PTR(usb4_router_1) + }; + + struct device *usb4_pcie[NUM_USB4_CONTROLLERS] = { + DEV_PTR(usb4_pcie_bridge_0), + DEV_PTR(usb4_pcie_bridge_1) + }; + + /* In coreboot the USB4 ports are first in order, but openSIL expects the opposite */ + struct device *usb2_ports[USB2_PORT_COUNT] = { + DEV_PTR(usb2_port2), + DEV_PTR(usb2_port3), + DEV_PTR(usb2_port4), + DEV_PTR(usb2_port5), + DEV_PTR(usb2_port6), + DEV_PTR(usb2_port7), + DEV_PTR(usb2_port0), + DEV_PTR(usb2_port1) + }; + + struct device *usb3_ports[USB3_PORT_COUNT] = { + DEV_PTR(usb3_port2), + DEV_PTR(usb3_port3), + DEV_PTR(usb3_port7) + }; + + struct device *usb4_xhci_ports[NUM_USB4_CONTROLLERS] = { + DEV_PTR(usb3_port0), + DEV_PTR(usb3_port1) + }; + + const struct usb_port_map { + uint8_t usb2_ports; + uint8_t usb3_ports; + } usb_port_map[NUM_XHCI_CONTROLLERS] = { + { 5, 2 }, + { 1, 1 }, + { 1, 1 }, + { 1, 1 } + }; + + const struct soc_amd_phoenix_config *soc_config = config_of_soc(); + const struct usb_phy_config *usb_phy = &soc_config->usb_phy; + FCHUSB_INPUT_BLK *fch_usb_data = SilFindStructure(SilContext, SilId_FchUsb, 0); if (!fch_usb_data) @@ -94,6 +150,86 @@ static void configure_usb(SIL_CONTEXT *SilContext) fch_usb_data->Xhci1Enable = is_dev_enabled(usb_ctrlr[1]); fch_usb_data->Usb4Host[0].Usb3HCDisable = !is_dev_enabled(usb_ctrlr[2]); fch_usb_data->Usb4Host[1].Usb3HCDisable = !is_dev_enabled(usb_ctrlr[3]); + fch_usb_data->Usb4Host[0].HostEnable = is_dev_enabled(usb4_rt[0]); + fch_usb_data->Usb4Host[1].HostEnable = is_dev_enabled(usb4_rt[1]); + fch_usb_data->Usb4Host[0].PcieAdpHidden = !is_dev_enabled(usb4_pcie[0]); + fch_usb_data->Usb4Host[1].PcieAdpHidden = !is_dev_enabled(usb4_pcie[1]); + if (fch_usb_data->Usb4Host[0].PcieAdpHidden) + fch_usb_data->Usb4Host[0].PcieTunnelingDisable = 1; + if (fch_usb_data->Usb4Host[1].PcieAdpHidden) + fch_usb_data->Usb4Host[1].PcieTunnelingDisable = 1; + + /* + * XHCI_OC structure is broken, it tries to fit u32 and u16 into single u32. + * It causes the memcpy to incorrectly assign USB3 OC pins. Also the OC pin map + * is not separate from USB2 ports, but simply follows the USB2 OC pin map and + * the offset depens on the port count, + */ + uint32_t oc_pins, mask, shift; + for (int i = 0; i < NUM_XHCI_CONTROLLERS; i++) { + oc_pins = 0xffffffff; + memcpy(&oc_pins, &soc_config->usb2_oc_pins[i], sizeof(soc_config->usb2_oc_pins[i])); + + mask = (1 << (usb_port_map[i].usb2_ports * 4)) - 1; + fch_usb_data->XhciOCpinSelect[i].OcPinSelect &= ~mask; + fch_usb_data->XhciOCpinSelect[i].OcPinSelect |= oc_pins & mask; + + oc_pins = 0xffffffff; + memcpy(&oc_pins, &soc_config->usb3_oc_pins[i], sizeof(soc_config->usb3_oc_pins[i])); + + mask = (1 << (usb_port_map[i].usb3_ports * 4)) - 1; + shift = usb_port_map[i].usb2_ports * 4; + fch_usb_data->XhciOCpinSelect[i].OcPinSelect &= ~(mask << shift); + fch_usb_data->XhciOCpinSelect[i].OcPinSelect |= (oc_pins & mask) << shift; + } + + for (int i = 0; i < (USB2_PORT_COUNT - NUM_USB4_CONTROLLERS); i++) { + if (!is_dev_enabled(usb2_ports[i])) + fch_usb_data->XhciUsb2PortDisable |= (1 << i); + } + + for (int i = 0; i < USB3_PORT_COUNT; i++) { + if (!is_dev_enabled(usb3_ports[i])) + fch_usb_data->XhciUsb3PortDisable |= (1 << i); + } + + /* USB4 ports have different bit shifts */ + if (!is_dev_enabled(usb2_ports[6])) + fch_usb_data->XhciUsb2PortDisable |= (1 << 8); + + if (!is_dev_enabled(usb2_ports[7])) + fch_usb_data->XhciUsb2PortDisable |= (1 << 12); + + if (!is_dev_enabled(usb4_xhci_ports[0])) { + fch_usb_data->XhciUsb3PortDisable |= (1 << 4); + fch_usb_data->Usb4Host[0].SSPortDisable |= 1; + } + + if (!is_dev_enabled(usb4_xhci_ports[1])) { + fch_usb_data->XhciUsb3PortDisable |= (1 << 6); + fch_usb_data->Usb4Host[1].SSPortDisable |= 1; + } + + fch_usb_data->XhciOcPolarityCfgLow = soc_config->polarity_cfg_low; + fch_usb_data->Usb3PortForceGen1 = soc_config->usb3_force_gen1.raw; + + if (!soc_config->usb_phy_custom) + return; + + usb_config.Version_Major = TACOMA_USB_STRUCT_MAJOR_VERSION; + usb_config.Version_Minor = TACOMA_USB_STRUCT_MINOR_VERSION; + usb_config.TableLength = sizeof(FCH_TC_USB_OEM_PLATFORM_TABLE); + + memcpy(usb_config.Usb3PhyPort, usb_phy->Usb3PhyPort, sizeof(usb_config.Usb3PhyPort)); + memcpy(usb_config.Usb20PhyPort, usb_phy->Usb2PhyPort, sizeof(usb_config.Usb20PhyPort)); + memcpy(usb_config.ComboPhyStaticConfig, usb_phy->ComboPhyStaticConfig, + sizeof(usb_config.ComboPhyStaticConfig)); + memcpy(usb_config.Reserved1, usb_phy->Usb4Phy, sizeof(usb_config.Reserved1)); + + usb_config.BatteryChargerEnable = usb_phy->BatteryChargerEnable; + usb_config.PhyP3CpmP4Support = usb_phy->PhyP3CpmP4Support; + + fch_usb_data->OemUsbConfigurationTable = (uintptr_t)&usb_config; } static void configure_ccx(SIL_CONTEXT *SilContext) @@ -139,10 +275,14 @@ WEAK_DEV_PTR(i3c_0); WEAK_DEV_PTR(i3c_1); WEAK_DEV_PTR(i3c_2); WEAK_DEV_PTR(i3c_3); +WEAK_DEV_PTR(hfp); +WEAK_DEV_PTR(hid_2); +WEAK_DEV_PTR(hid); +WEAK_DEV_PTR(lpc_bridge); #define FCH_DEV_ENABLE(dev, aoac_bit) \ fch_data->FchRunTime.FchDeviceEnableMap |= \ - (is_dev_enabled(DEV_PTR(dev)) ? aoac_bit : 0) + (is_dev_enabled(DEV_PTR(dev)) ? (1ul << aoac_bit) : 0) static void configure_fch_acpi(SIL_CONTEXT *SilContext) { @@ -179,7 +319,9 @@ static void configure_fch_acpi(SIL_CONTEXT *SilContext) fch_data->WdtEnable = false; - fch_data->FchRunTime.FchDeviceEnableMap = 0; + /* eSPI always enabled (bit 27) */ + fch_data->FchRunTime.FchDeviceEnableMap = (1 << 27); + FCH_DEV_ENABLE(lpc_bridge, 4); FCH_DEV_ENABLE(i2c_0, FCH_AOAC_DEV_I2C0); FCH_DEV_ENABLE(i2c_1, FCH_AOAC_DEV_I2C1); FCH_DEV_ENABLE(i2c_2, FCH_AOAC_DEV_I2C2); @@ -193,6 +335,9 @@ static void configure_fch_acpi(SIL_CONTEXT *SilContext) FCH_DEV_ENABLE(i3c_1, FCH_AOAC_DEV_I3C1); FCH_DEV_ENABLE(i3c_2, FCH_AOAC_DEV_I3C2); FCH_DEV_ENABLE(i3c_3, FCH_AOAC_DEV_I3C3); + FCH_DEV_ENABLE(hfp, 29); + FCH_DEV_ENABLE(hid_2, 30); + FCH_DEV_ENABLE(hid, 31); } void setup_opensil(void)