B850 support part4

src/device/oprom/x86emu/debug.h

@@ -40,6 +40,8 @@
 #define __X86EMU_DEBUG_H
 
 #include <console/console.h>
+#include <string.h>
+#include <stdio.h>
 
 /*---------------------- Macros and type definitions ----------------------*/
 

src/device/oprom/yabel/biosemu.c

@@ -55,6 +55,7 @@
 #if CONFIG(X86EMU_DEBUG_TIMINGS)
 #include <timer.h>
 struct mono_time zero;
+struct mono_time now;
 #endif
 
 static X86EMU_memFuncs my_mem_funcs = {

src/device/oprom/yabel/debug.h

@@ -39,6 +39,7 @@
 
 #if CONFIG(X86EMU_DEBUG_TIMINGS)
 extern struct mono_time zero;
+extern struct mono_time now;
 #endif
 extern u32 debug_flags;
 // from x86emu...needed for debugging
@@ -100,7 +101,7 @@ static inline void set_ci(void) {};
 // to be executed, since the x86emu advances CS:IP _before_ actually executing an instruction
 
 #if CONFIG(X86EMU_DEBUG_TIMINGS)
-#define DEBUG_PRINTF_CS_IP(_x...) DEBUG_PRINTF("[%08lx]%x:%x ", (current_time_from(&zero)).microseconds, M.x86.R_CS, M.x86.R_IP); DEBUG_PRINTF(_x);
+#define DEBUG_PRINTF_CS_IP(_x...) timer_monotonic_get(&now); DEBUG_PRINTF("[%lld]%x:%x ", mono_time_diff_microseconds(&zero, &now), M.x86.R_CS, M.x86.R_IP); DEBUG_PRINTF(_x);
 #else
 #define DEBUG_PRINTF_CS_IP(_x...) DEBUG_PRINTF("%x:%x ", M.x86.R_CS, M.x86.R_IP); DEBUG_PRINTF(_x);
 #endif

src/mainboard/msi/ms7e56/devicetree.cb

@@ -45,6 +45,160 @@ chip soc/amd/phoenix
 
 	register "pspp_policy" = "DXIO_PSPP_DISABLED"
 
+	register "usb_phy_custom" = "true"
+
+	register "usb_phy" = "{
+		.Usb2PhyPort[0] = {
+			.compdistune = 0x1,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[1] = {
+			.compdistune = 0x1,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[2] = {
+			.compdistune = 0x1,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[3] = {
+			.compdistune = 0x1,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[4] = {
+			.compdistune = 0x1,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[5] = {
+			.compdistune = 0x1,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[6] = {
+			.compdistune = 0x1,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[7] = {
+			.compdistune = 0x1,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb3PhyPort[0] = {
+			.tx_term_ctrl = 0x2,
+			.rx_term_ctrl = 0x2,
+			.tx_vboost_lvl_en = 0x0,
+			.tx_vboost_lvl = 0x5,
+		},
+		.Usb3PhyPort[1] = {
+			.tx_term_ctrl = 0x2,
+			.rx_term_ctrl = 0x2,
+			.tx_vboost_lvl_en = 0x0,
+			.tx_vboost_lvl = 0x5,
+		},
+		.Usb3PhyPort[2] = {
+			.tx_term_ctrl = 0x2,
+			.rx_term_ctrl = 0x2,
+			.tx_vboost_lvl_en = 0x0,
+			.tx_vboost_lvl = 0x5,
+		},
+		.ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_ONLY,
+		.ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_ONLY,
+		.ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_ONLY,
+	}"
+
+	register "usb3_force_gen1" = "{
+		.port0 = 1,
+		.port2 = 1,
+	}"
+
+	register "polarity_cfg_low" = "true"
+
+	register "usb2_oc_pins[0]" = "{ 0x2, 0x3, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
+	register "usb2_oc_pins[1]" = "{ 0x3, 0x3, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
+	register "usb2_oc_pins[2]" = "{ 0x1, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
+	register "usb2_oc_pins[3]" = "{ 0x1, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
+	register "usb3_oc_pins[0]" = "{ 0x2, 0x3, 0xf, 0xf }"
+	register "usb3_oc_pins[1]" = "{ 0x3, 0xf, 0xf, 0xf }"
+	register "usb3_oc_pins[2]" = "{ 0x1, 0xf, 0xf, 0xf }"
+	register "usb3_oc_pins[3]" = "{ 0x1, 0xf, 0xf, 0xf }"
+
 	device domain 0 on
 		device ref iommu on end
 

src/soc/amd/phoenix/Makefile.mk

@@ -16,6 +16,9 @@ all_x86-y	+= gpio.c
 all_x86-y	+= i3c.c
 all_x86-y	+= uart.c
 
+all_x86-y	+= lpc.c
+smm-y		+= lpc.c
+
 bootblock-y	+= early_fch.c
 bootblock-y	+= espi_util.c
 

src/soc/amd/phoenix/chip.h

@@ -106,8 +106,56 @@ struct soc_amd_phoenix_config {
 	} pspp_policy;
 
 	bool usb_phy_custom;
+
 	struct usb_phy_config usb_phy;
 
+	/*
+	 * XHCI0 has 5 USB2 ports
+	 * XHCI1 has 1 USB2 port
+	 * USB4 XHCI has 1 USB2 port each
+	 */
+	struct {
+		uint8_t port0 : 4;
+		uint8_t port1 : 4;
+		uint8_t port2 : 4;
+		uint8_t port3 : 4;
+		uint8_t port4 : 4;
+		uint8_t port5 : 4;
+		uint8_t port6 : 4;
+		uint8_t port7 : 4;
+	} usb2_oc_pins[4];
+	/*
+	 * XHCI0 has 2 USB3 ports
+	 * XHCI1 has 1 USB3 port
+	 * USB4 XHCI has 1 USB3 port each
+	 */
+	struct {
+		uint8_t port0 : 4;
+		uint8_t port1 : 4;
+		uint8_t port2 : 4;
+		uint8_t port3 : 4;
+	} usb3_oc_pins[4];
+
+	bool polarity_cfg_low;
+
+	/*
+	 * Force gen1 for XHCI.
+	 * bits [1:0] for XHCI0 port 0-1
+	 * bit 2 for XHCI1 port 0
+	 * bit 3 for first USB4 XHCI port 0
+	 * bit 4 for second USB4 XHCI port 0
+	 */
+	union {
+		struct {
+			uint8_t port0 : 1;
+			uint8_t port1 : 1;
+			uint8_t port2 : 1;
+			uint8_t port3 : 1;
+			uint8_t port4 : 1;
+		};
+		uint8_t raw;
+	} usb3_force_gen1;
+
 #if !CONFIG(PLATFORM_USES_FSP2_0)
 	struct ddi_descriptor ddi[DDI_DESCRIPTOR_COUNT];
 #endif

src/soc/amd/phoenix/chip_opensil.h

@@ -60,15 +60,6 @@ struct fch_usb3_phy {
 	uint8_t tx_vboost_lvl;		///< TX_VBOOST_LVL
 };
 
-#define USB0_PORT0	0
-#define USB0_PORT1	1
-#define USB0_PORT2	1
-#define USB0_PORT3	3
-#define USB1_PORT0	(0<<2)
-#define USB1_PORT1	(1<<2)
-#define USB1_PORT2	(1<<2)
-#define USB1_PORT3	(3<<2)
-
 #define USB_COMBO_PHY_MODE_USB_C	0
 #define USB_COMBO_PHY_MODE_USB_ONLY	1
 #define USB_COMBO_PHY_MODE_USB_DPM	2
@@ -80,6 +71,7 @@ struct usb_phy_config {
 	uint8_t			BatteryChargerEnable;              ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
 	uint8_t			PhyP3CpmP4Support;                 ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
 	uint8_t			ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP
+	uint8_t			Usb4Phy[USBC_COMBO_PHY_COUNT];     /// bit[3:0]-USB4 Port0, bit[7:4]-USB4 Port1
 };
 
 #endif /* PHOENIX_CHIP_OPENSIL_H */

src/soc/amd/phoenix/chipset_opensil.cb

@@ -1,4 +1,14 @@
 chip soc/amd/phoenix
+
+	register "usb2_oc_pins[0]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
+	register "usb2_oc_pins[1]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
+	register "usb2_oc_pins[2]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
+	register "usb2_oc_pins[3]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
+	register "usb3_oc_pins[0]" = "{ 0xf, 0xf, 0xf, 0xf }"
+	register "usb3_oc_pins[1]" = "{ 0xf, 0xf, 0xf, 0xf }"
+	register "usb3_oc_pins[2]" = "{ 0xf, 0xf, 0xf, 0xf }"
+	register "usb3_oc_pins[3]" = "{ 0xf, 0xf, 0xf, 0xf }"
+
 	device cpu_cluster 0 on
 		ops amd_cpu_bus_ops
 	end
@@ -160,6 +170,9 @@ chip soc/amd/phoenix
 		device pci 18.7 alias data_fabric_7 on ops amd_data_fabric_ops end
 	end
 
+	device mmio 0xfec11000 alias hfp   off end
+	device mmio 0xfec12000 alias hid_2 off end
+	device mmio 0xfec13000 alias hid   off end
 	device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end
 	device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end
 	device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end

src/soc/amd/phoenix/fch.c

@@ -144,6 +144,7 @@ static void cgpll_clock_gate_init(void)
 	misc_write32(MISC_CLKGATEDCNTL, t);
 
 	t = misc_read32(MISC_CGPLL_CONFIGURATION0);
+	t |= USB_PHY_CMCLK_ZSTATE_DIS;
 	t |= USB_PHY_CMCLK_S3_DIS;
 	t |= USB_PHY_CMCLK_S0I3_DIS;
 	t |= USB_PHY_CMCLK_S5_DIS;

src/soc/amd/phoenix/include/soc/southbridge.h

@@ -93,6 +93,7 @@
 #define   XTAL_PAD_S3_TURNOFF_EN	BIT(20)
 #define   XTAL_PAD_S5_TURNOFF_EN	BIT(21)
 #define MISC_CGPLL_CONFIGURATION0	0x30
+#define   USB_PHY_CMCLK_ZSTATE_DIS	BIT(1)
 #define   USB_PHY_CMCLK_S3_DIS		BIT(8)
 #define   USB_PHY_CMCLK_S0I3_DIS	BIT(9)
 #define   USB_PHY_CMCLK_S5_DIS		BIT(10)

src/soc/amd/phoenix/lpc.c

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/lpc.h>
+#include <amdblocks/spi.h>
+
+void soc_lpc_tpm_decode_spi(void)
+{
+	/* SoC-specific SPI TPM setting */
+	spi_write32(SPI_CNTRL0, spi_read32(SPI_CNTRL0) | (1 << 13));
+	spi_write32(SPI100_HOST_PREF_CONFIG, spi_read32(SPI100_HOST_PREF_CONFIG) | (1 << 25));
+}