From 5e5f7b7e1f7f19ae6f077d06334d3ddba4db8ae8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Filip=20Go=C5=82a=C5=9B?= Date: Wed, 20 May 2026 15:03:49 +0200 Subject: [PATCH] mb/protectli/vault_cml: Enable FP_RST button signal GPIO input MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The button sits on a single function pin of the IT8786. Enabled the chip's GPIO block in devicetree.cb, and configured the GP80 pin as an input in bootblock. Mapped to /dev/port at `0xa07` bit `2`. Upstream-Status: Inappropriate [Dasharo downstream] Signed-off-by: Filip Gołaś --- src/mainboard/protectli/vault_cml/bootblock.c | 12 ++++++++++++ src/mainboard/protectli/vault_cml/devicetree.cb | 4 +++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/src/mainboard/protectli/vault_cml/bootblock.c b/src/mainboard/protectli/vault_cml/bootblock.c index 82c46f985f3..2fad95cfc36 100644 --- a/src/mainboard/protectli/vault_cml/bootblock.c +++ b/src/mainboard/protectli/vault_cml/bootblock.c @@ -1,14 +1,24 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include +#include #include #include "gpio.h" #define UART_DEV PNP_DEV(0x2e, IT8784E_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8784E_GPIO) +static void ite_set_gpio_iobase(u16 iobase) +{ + pnp_enter_conf_state(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + pnp_set_iobase(GPIO_DEV, PNP_IDX_IO1, iobase); + pnp_exit_conf_state(GPIO_DEV); +} + void bootblock_mainboard_early_init(void) { /* CLKIN freq 24MHz, Ext CLKIN for Watchdog, Internal VCC_OK */ @@ -25,6 +35,8 @@ void bootblock_mainboard_early_init(void) ite_delay_pwrgd3(GPIO_DEV); ite_kill_watchdog(GPIO_DEV); ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); + ite_gpio_setup(GPIO_DEV, 80 , ITE_GPIO_INPUT, ITE_GPIO_SIMPLE_IO_MODE, ITE_GPIO_PULLUP_ENABLE); + ite_set_gpio_iobase(0xa00); } void bootblock_mainboard_init(void) diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index b04d845b4fb..c5fccfad4eb 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -210,7 +210,9 @@ chip soc/intel/cannonlake end device pnp 2e.5 off end # Keyboard device pnp 2e.6 off end # Mouse - device pnp 2e.7 off end # GPIO + device pnp 2e.7 on + io 0x62 = 0xa00 + end # GPIO device pnp 2e.a off end # CIR end chip drivers/pc80/tpm