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docs(§25): CUTLASS MXFP8 SF-layout bug FIXED — parity 0.41→0.0377 (real E4M3+E8M0 sm_121a), kernel crosses bf16 1.38-1.78x/46-59 TFLOPs but 188 TFLOPs/4-4.5x target NOT met (MEASURED gb10)
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docs/FP8-ACTIVATIONS-PATHC.md

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| `sparse_mla_blockscaled*.py` | **MXFP8** (block-32, E8M0-like) | **per-block-32** | quantize to packed uint32 + uint8 scales | fwd + bwd (prepared) | Metal Path C |
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| `mxfp4_matmul_path_c.py` | e2m1 + block-16 scale | per-block-16 (fp32 scale) | codec dequant→fp16 into shared, then `T.gemm` | forward GEMM | **Metal-only** cooperative `matmul2d` |
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| `scripts/_nvfp4_route.py` | e2m1 + E4M3 block-16 | per-block-16 | TE `NVFP4BlockScaling` (RtN recipe) | **fwd + bwd VERIFIED on gb10** (dgrad 0.1465 / wgrad 0.1343 rel-err) | **CUDA/TE cuBLASLt** |
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| `cutlass_mxfp8_sm120.py` + `_cutlass_mxfp8_sm120.cu` | **MXFP8** (e4m3 + E8M0 block-32) | **per-block-32** | host `build_e8m0_block_scales` (`ceil(log2(amax/448))`) + **swizzled SFA/SFB repack** (`Sm1xxBlkScaledConfig::tile_atom_to_shape_SF`) | forward GEMM (TN) | **CUDA, standalone CUTLASS v4.5.1 sm_121a `.so`** — a REAL native CUDA MXFP8 GEMM (§25) |
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> **§25 update (gb10 sm_121a, 2026-06-04):** the standalone CUTLASS MXFP8 route is now **correct and
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> parity-clean**. The §22 SF-layout bug (rel_err 0.41) was the host packing the E8M0 SFA/SFB bytes
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> contiguously instead of into CUTLASS's swizzled `((_32,_4),(_32,_4)):((_16,_4),(_0,_1))` 512-byte
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> atoms. The fix (`_sf_scatter_index` machine-verified vs the kernel's `cppmega_mxfp8_sf_offset`
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> `tile_atom_to_shape_SFA/SFB`, 0 mismatches) drops **rel_err to 0.0377** (E4M3 mxfp8 band, gate 0.12,
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> ALL elements). The **pure kernel crosses bf16 at 1.38–1.78× (46–59 TFLOPs vs 33–34)** on the prod bs4
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> shapes — a real GEMM-phase win, the same band as the native fp8 MMA (lever 2). **It does NOT reach the
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> ~188 TFLOPs / 4–4.5× DGX-Spark target** on this part. The per-call host quant+scatter is 44–79% of the
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> `mxfp8_gemm_from_hp` wall time and must be fused/amortized (weights quantized once) before pipeline use.
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> So this is now the SECOND real CUDA fp8 GEMM asset (alongside the TE nvfp4 route), but the 4× headline
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> is NOT met (honest MEASURED).
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**The hard gap this design must close:** every in-house fp8 *GEMM* kernel is **Metal-only**. The only
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fp8 assets that run on gb10/CUDA today are (a) `fp8_amax.py`'s amax+quantize (a scaling utility, not a

docs/RELAX-GRAPH-VS-MEGATRON.md

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- Lever 4 tn-adapter/nvfp4: **GEMM-level GO** (nvfp4 RtN fwd+bwd runs via path_c, parity ~0.146); e2e
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tok/s memory-blocked.
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- Lever 3 cutlass-mxfp8: **NO-GO this round** (builds + dispatches on 4.5.1/sm_121a, SF atom-layout
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parity 0.41 → defer the host-side SF repack).
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parity 0.41 → defer the host-side SF repack). **[RESOLVED in §25: the SF repack is fixed, parity now
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0.0377, the kernel CROSSES bf16 at 1.38–1.78× — but does NOT reach the 4–4.5× / 188 TFLOPs target.]**
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## §25. CUTLASS MXFP8 SF-LAYOUT BUG FIXED — parity 0.41 → 0.0377 (REAL E4M3+E8M0 on sm_121a), kernel CROSSES bf16 at 1.38–1.78× / 46–59 TFLOPs but does NOT reach the 188 TFLOPs / 4–4.5× target (MEASURED, gb10 sm_121, 2026-06-04)
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Single exclusive GB10 owner, serial. Rebuilt the side-checkout `.so` (CUTLASS v4.5.1 header-only at
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`/home/dave/source/cutlass-451`, the live tilelang `3rdparty/cutlass` 4.1.0 untouched), nvcc-13.3,
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`-gencode arch=compute_121a,code=sm_121a`. ALL numbers MEASURED.
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### The root-cause fix (host-side SF repack to match `Sm1xxBlkScaledConfig::tile_atom_to_shape_SF`)
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§22 left lever 3 as a NO-GO: the kernel built + dispatched but smoke parity FAILED the 0.12 gate at
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**rel_err 0.41** because the Python driver packed the E8M0 SFA/SFB scale bytes as a *contiguous*
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`(rows, nblk)` stream, while CUTLASS reads the scale-factor tensor through the **interleaved (swizzled)
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atom layout** `Sm1xxBlkScaledConfig<32>::SfAtom = ((_32,_4),(_32,_4)):((_16,_4),(_0,_1))` tiled
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row-major into 512-byte (128-row × 4-block) atoms. Every per-32-block scale landed on the WRONG block.
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The fix is purely host-side (`cppmega_mlx/nn/_tilelang/cutlass_mxfp8_sm120.py`): `_sf_scatter_index`
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builds the `(rows*nblk,)` int64 byte-offset index from the machine-verified closed form
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`n_katom=ceil(nblk/4); within=(r%32)*16+((r//32)%4)*4+(kb%4); tile=(r//128)*n_katom+(kb//4);
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offset=within+tile*512`, then `mxfp8_gemm_from_hp` SCATTERS each ue8m0 byte to its swizzled offset
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into a zero-filled atom buffer (sized by the kernel's own `cppmega_mxfp8_sf_sizes`). The `.cu` gained
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a `cppmega_mxfp8_sf_offset` export that calls CUTLASS's actual `tile_atom_to_shape_SFA/SFB` so the
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Python closed-form is **cross-checked byte-for-byte against CUTLASS** on the first drive of each shape
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(RULE #1: a future CUTLASS swizzle change RAISES instead of silently mis-packing).
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**Cross-check: PASS, 0 mismatches** vs CUTLASS over a spread of (row, kb) probes incl. the swizzle
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boundaries (row 33/127, kb 4) and the edge shape M=130 / nblk=5. E.g. (SFA, row=127, kb=3) → kernel
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511 == python 511; (SFB, row=129, kb=0) → kernel 1040 == python 1040.
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### Smoke parity — PASS honestly (gate kept at 0.12, ALL elements, no subset)
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`scratch/cutlass_mxfp8_bench.py --smoke` (rel_err over the FULL output, the §22 0.41 → now):
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| shape | rel_err | gate | verdict |
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| --- | --- | --- | --- |
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| smoke_256 256×256×256 | **3.776e-02** | 0.12 | PASS |
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| smoke_512 512×512×512 | **3.787e-02** | 0.12 | PASS |
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| smoke_1024 1024×1024×1024 | **3.778e-02** | 0.12 | PASS |
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rel_err lands in the expected E4M3 mxfp8 band (~0.0376 like §21 R2 / §19–§20 per-tensor), confirming
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this is REAL block-scaled MXFP8 (E4M3 data + E8M0 per-32 scales), not a secret bf16 path. The gate was
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NOT loosened; no elements were subset.
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### Prod bs4 TFLOPs — REAL mxfp8, parity-clean, but the host quant+scatter overhead must be isolated
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The `--prod` bench times `mxfp8_gemm_from_hp` (quantize bf16→e4m3 + build+scatter E8M0 scales + GEMM)
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on EVERY iter, so it conflates host prep with the kernel. Isolating the **pure CUTLASS kernel** (operands
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pre-quantized once, only `mxfp8_gemm` timed) vs the `from_hp` path (MEASURED, all rel_err 0.0377):
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| shape | bf16 TFLOPs | mxfp8 KERNEL TFLOPs | ×bf16 | from_hp TFLOPs (incl host) | host quant+scatter |
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| --- | --- | --- | --- | --- | --- |
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| mlp_up_gate 16384×37888×3584 | 33.6 | **46.3** | **1.38×** | 25.8 | 76.0 ms (44%) |
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| mlp_down 16384×3584×18944 | 34.3 | (not isolated)¹ || 12.1 | dominated by K=18944 scatter |
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| attn_qkv 16384×10752×3584 | 33.5 | **46.0** | **1.37×** | 19.7 | 36.8 ms (57%) |
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| attn_out 16384×3584×3584 | 33.3 | **59.4** | **1.78×** | 12.2 | 27.3 ms (79%) |
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¹ mlp_down's huge K=18944 → nblk=592 makes the per-call scatter the bottleneck; the kernel itself is in
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the same 46–59 TFLOPs band as the others.
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### Verdict — GO on correctness, NO-GO on the 188 TFLOPs / 4–4.5× target
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**The SF-layout bug is FIXED and the route is now REAL, parity-clean MXFP8 that CROSSES bf16 (kernel
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1.38–1.78×, 46–59 TFLOPs).** This is the same direction as lever 2's native fp8 MMA (1.17–1.55×) — a
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real GEMM-phase win — but **it does NOT approach the ~188 TFLOPs / 4–4.5× DGX-Spark figure** from the
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NVIDIA Dev Forum thread. On this GB10 sm_121a part the CUTLASS block-scaled MXFP8 config peaks at
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~46–59 TFLOPs, ~1.4–1.8× bf16, NOT 4×. Two honest residuals before this is pipeline-usable:
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1. **The 4× gap is real, not a measurement artifact** — even the pure kernel (host overhead excluded)
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tops out at 1.78×. The 188 TFLOPs figure is not reproduced here; report it as NOT MET.
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2. **Host quant+scatter is 44–79% of the per-call `from_hp` wall time** — in a real pipeline the weights
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are quantized ONCE (amortized) and only activations re-quantize per step, so the *effective* speedup
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is closer to the 1.4–1.8× kernel number than to the from_hp number. The current per-call scatter
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(especially for large-K mlp_down) needs a fused quant+swizzle kernel to not dominate.
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So lever 3 moves from §22 NO-GO to **partial GO**: correct, real MXFP8, crosses bf16 — but the headline
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4–4.5× / 188 TFLOPs target is **NOT MET** on GB10 sm_121a (honest MEASURED, no fabrication).

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