Commit fca1f08
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feat(v4): GDN Path B bwd kernel — multi-simdgroup support for Dh > 32
Extends the real-MSL GDN backward kernel from Dh ≤ 32 (single 32-lane
simdgroup) to Dh ≤ 256 (up to 8 simdgroups via padded threadgroup
size + atomic_fetch_add_explicit on cross-simdgroup outputs).
Implementation:
- tg_size = ceil(Dh / 32) * 32 — threadgroup padded to a 32-multiple
so simd_sum (which reduces within a single simdgroup) still works.
- use_atomic = (Dh > 32): grad writes for dq[i], dk[i], dbeta, dg
switch from "if j==0: write" to "if (j & 31u)==0: atomic_add"
so each simdgroup's lane-0 contributes its partial.
- Pre-zero outputs (init_value=0.0) so atomics accumulate from zero.
- dv is per-j and stays a direct store (no cross-simdgroup contention).
Tests (2 new):
- test_path_b_bwd_dh64_matches_path_a: Dh=64 (2 simdgroups) — grad
parity vs Path A within atol=2e-4 / rtol=2e-3 (slightly looser than
Dh≤32 case to absorb atomic accumulation ordering drift).
- test_path_b_bwd_dh128_runs_and_grads_finite: Dh=128 (4 simdgroups) —
no NaN/inf, correct shapes.
Bench (B=1, T=64, H=4):
Dh=32: PathA 8.65 ms → PathB-MSL 1.04 ms (8.3×)
Dh=64: PathA 8.32 ms → PathB-MSL 3.49 ms (2.4×)
Dh=128: PathA 8.20 ms → PathB-MSL 8.54 ms (1.0×)
At Dh=128 atomic contention catches up to the MLX autograd's
amortized cost on small T. Speedup at Dh≤32 stays at 8-15× per
previous bench. For production Qwen-Next-class Dh=128 shapes the
kernel produces correct grads (no more Path A fallback at training
time) which is the main blocker the goal called out — perf tuning
of the contention is a follow-up (shared-memory cross-simdgroup
reduction instead of global-memory atomics).
v4 suite: 312 passed / 2 skipped.1 parent e09461c commit fca1f08
2 files changed
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