-
Notifications
You must be signed in to change notification settings - Fork 0
Expand file tree
/
Copy pathpipeline.cr.mti
More file actions
140 lines (126 loc) · 8.81 KB
/
pipeline.cr.mti
File metadata and controls
140 lines (126 loc) · 8.81 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
{C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/XRegs.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/XRegs.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity xregs
-- Compiling architecture behavior of XRegs
} {} {}} {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/control.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/control.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity ControlModule
-- Compiling architecture cont of ControlModule
} {} {}} {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/Mux.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/Mux.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity MUX_PC_Module
-- Compiling architecture df of MUX_PC_Module
-- Compiling entity MUX_ALU_Module
-- Compiling architecture df of MUX_ALU_Module
-- Compiling entity MUX_XREG_Module
-- Compiling architecture df of MUX_XREG_Module
} {} {}} {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/PC.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/PC.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity pc
-- Compiling architecture pc_arch of pc
} {} {}} {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/immGen.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/immGen.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity immGen
-- Compiling architecture immGen_arch of immGen
} {} {}} {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/barramentos.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/barramentos.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity InstructionFetchDecodePipeline
-- Compiling architecture df of InstructionFetchDecodePipeline
-- Compiling entity InstructionDecodeExecutePipeline
-- Compiling architecture df of InstructionDecodeExecutePipeline
-- Compiling entity ExecuteMemoryPipeline
-- Compiling architecture df of ExecuteMemoryPipeline
-- Compiling entity MemoryWriteBackPipeline
-- Compiling architecture df of MemoryWriteBackPipeline
} {} {}} {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/CPU.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/CPU.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity CPU
-- Compiling architecture structure_pipeline of CPU
} {} {}} {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/testbench.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/testbench.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity testbench
-- Compiling architecture arch of testbench
} {} {}} {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/control_ula.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/control_ula.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity control_ula
-- Compiling architecture control_ula_arch of control_ula
} {} {}} {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/ulaRv.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/ulaRv.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity ulaRv
-- Compiling architecture behavior of ulaRv
} {} {}} {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/memory_data.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/memory_data.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity memory_data
-- Compiling architecture mem_arch of memory_data
} {} {}} {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/adders.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/adders.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity adder_module
-- Compiling architecture df of adder_module
-- Compiling entity ADDER_PC_IMM_Module
-- Compiling architecture df of ADDER_PC_IMM_Module
} {} {}} {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/PC_control.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/PC_control.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity pc_control
-- Compiling architecture arch_ctr of pc_control
} {} {}} {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/memory_inst.vhd} {1 {vcom -work work -2002 -explicit -stats=none {C:/Users/david/OneDrive/Documentos/Faculdade/2022.2/Organizacao e Arquitetura de Computadores/Pipeline RiscV/memory_inst.vhd}
Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Loading package std_logic_textio
-- Compiling entity memory_inst
-- Compiling architecture memI_arch of memory_inst
} {} {}}