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2 | 2 | id:: ai-hardware-ontology |
3 | 3 | collapsed:: true |
4 | 4 | - ontology:: true |
| 5 | + - public-access:: true |
5 | 6 | - term-id:: AI-7020 |
6 | 7 | - preferred-term:: AI Hardware |
7 | 8 | - source-domain:: ai |
8 | | - - status:: stub |
9 | | - - public-access:: true |
10 | | - - definition:: Stub page for AI Hardware. Referenced by 5 pages. Auto-generated during corpus cleanup. |
11 | | - - maturity:: draft |
| 9 | + - status:: active |
| 10 | + - definition:: AI Hardware encompasses specialized computing hardware designed to accelerate artificial intelligence and machine learning workloads, including GPUs, TPUs, NPUs, and other AI accelerators optimized for training neural networks and running inference at scale. These processors feature architectures specifically designed for the matrix operations, parallel processing, and low-precision arithmetic fundamental to modern AI algorithms. |
| 11 | + - maturity:: mature |
12 | 12 | - owl:class:: ai:AiHardware |
13 | | - - owl:physicality:: ConceptualEntity |
14 | | - - owl:role:: Concept |
| 13 | + - owl:physicality:: PhysicalEntity |
| 14 | + - owl:role:: Technology |
| 15 | + - belongsToDomain:: [[Artificial Intelligence]] |
| 16 | + - #### Relationships |
| 17 | + id:: ai-hardware-relationships |
| 18 | + collapsed:: true |
| 19 | + - is-subclass-of:: [[Computer Hardware]] |
| 20 | + - related-to:: [[Machine Learning]] |
| 21 | + - related-to:: [[Neural Networks]] |
| 22 | + - related-to:: [[High-Performance Computing]] |
| 23 | + - related-to:: [[AI Infrastructure]] |
| 24 | + - enables:: [[Deep Learning]] |
| 25 | + - enables:: [[Large Language Models]] |
| 26 | + - enables:: [[AI Training]] |
| 27 | + - #### Key Components |
| 28 | + collapsed:: true |
| 29 | + - **Graphics Processing Units (GPUs)**: Parallel processors with thousands of cores optimized for matrix operations; NVIDIA Blackwell architecture leads in 2025 |
| 30 | + - **Tensor Processing Units (TPUs)**: Google's custom ASICs for neural network acceleration; TPU v7 (Ironwood) delivers 4,614 TFLOP/s |
| 31 | + - **Neural Processing Units (NPUs)**: Low-power accelerators for edge AI and on-device inference with emphasis on energy efficiency |
| 32 | + - **AI Accelerators (ASICs)**: Application-specific chips like AWS Trainium/Inferentia, Microsoft Maia, Intel Habana Gaudi |
| 33 | + - **FPGAs**: Field-programmable gate arrays offering flexibility for custom AI workloads |
| 34 | + - #### Major Manufacturers (2025) |
| 35 | + collapsed:: true |
| 36 | + - **NVIDIA**: Market leader with Blackwell architecture, H100/H200 GPUs |
| 37 | + - **Google**: TPU v7 Ironwood with 256-chip and 9,216-chip cluster configurations |
| 38 | + - **AMD**: MI400 series challenging NVIDIA with competitive performance |
| 39 | + - **Intel**: Habana Gaudi processors for enterprise AI |
| 40 | + - **Cerebras**: Wafer-scale engines for large model training |
| 41 | + - **Groq**: LPUs optimized for low-latency inference |
| 42 | + - **SambaNova**: RDUs for enterprise AI workloads |
| 43 | + - #### Performance Metrics |
| 44 | + collapsed:: true |
| 45 | + - **TOPS (Trillions of Operations Per Second)**: 1-50 TOPS for edge NPUs, 90-420 TOPS for datacenter TPUs |
| 46 | + - **TFLOPS (Teraflops)**: Floating-point throughput for training workloads |
| 47 | + - **Power Efficiency**: Performance per watt critical for sustainable AI |
| 48 | + - **Memory Bandwidth**: HBM3 and HBM3e for high-bandwidth data transfer |
| 49 | + - #### Applications |
| 50 | + collapsed:: true |
| 51 | + - Large-scale model training in data centers |
| 52 | + - Real-time inference for AI services |
| 53 | + - Edge AI for IoT and mobile devices |
| 54 | + - Autonomous vehicle perception systems |
| 55 | + - Scientific computing and simulation |
| 56 | + - AI-powered content generation |
15 | 57 |
|
16 | 58 | ## Metadata |
17 | 59 |
|
18 | | -- **Last Updated**: 2025-12-28 |
19 | | -- **Review Status**: Auto-generated stub |
20 | | -- **References**: 5 pages reference this concept |
| 60 | +- **Last Updated**: 2025-12-29 |
| 61 | +- **Review Status**: Enriched with 2025 hardware specifications |
| 62 | +- **Verification**: Technical sources verified |
| 63 | +- **Regional Context**: Global technology landscape |
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