Skip to content

Commit a0abe3c

Browse files
abhinav92003abhinav92003
authored
i#7157 dyn inject: Add switch injection count to schedule_stats (#7301)
Adds the count of instances where the context switch sequence was injected to the schedule_stats tool output. Modifies the switch_insertion test to use schedule_stats instead of basic_counts. This helps reveal a bug in context switch trace template dynamic injection logic that causes the injection to happen many more times than the context switch events. This diff is split out from #7302 which fixes the above bug. Issue: #7157
1 parent 81ac8e5 commit a0abe3c

8 files changed

Lines changed: 49 additions & 10 deletions

File tree

‎clients/drcachesim/common/memtrace_stream.h‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/* **********************************************************
2-
* Copyright (c) 2022-2024 Google, Inc. All rights reserved.
2+
* Copyright (c) 2022-2025 Google, Inc. All rights reserved.
33
* **********************************************************/
44

55
/*
@@ -112,6 +112,10 @@ class memtrace_stream_t {
112112
* inputs from being scheduled onto an output.
113113
*/
114114
SCHED_STAT_HIT_OUTPUT_LIMIT,
115+
/**
116+
* Counts the instances when the context switch sequence was injected.
117+
*/
118+
SCHED_STAT_KERNEL_SWITCH_SEQUENCE_INJECTIONS,
115119
/** Count of statistic types. */
116120
SCHED_STAT_TYPE_COUNT,
117121
};

‎clients/drcachesim/scheduler/scheduler_impl.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2308,6 +2308,8 @@ scheduler_impl_tmpl_t<RecordType, ReaderType>::set_cur_input(
23082308
// XXX: These will appear before the top headers of a new thread which is slightly
23092309
// odd to have regular records with the new tid before the top headers.
23102310
if (!switch_sequence_[switch_type].empty()) {
2311+
++outputs_[output]
2312+
.stats[memtrace_stream_t::SCHED_STAT_KERNEL_SWITCH_SEQUENCE_INJECTIONS];
23112313
for (int i = static_cast<int>(switch_sequence_[switch_type].size()) - 1;
23122314
i >= 0; --i) {
23132315
RecordType record = switch_sequence_[switch_type][i];

‎clients/drcachesim/tests/core_serial.templatex‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ Total counts:
88
106490 instructions per context switch
99
6 voluntary context switches
1010
0 direct context switches
11+
0 context switch sequence injections
1112
100.00% voluntary switches
1213
0.00% direct switches
1314
4 switches input-to-input

‎clients/drcachesim/tests/schedule_stats_nopreempt.templatex‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ Total counts:
88
106490 instructions per context switch
99
6 voluntary context switches
1010
0 direct context switches
11+
0 context switch sequence injections
1112
100\.00% voluntary switches
1213
0\.00% direct switches
1314
5 switches input-to-input
@@ -45,6 +46,7 @@ Core #0 counts:
4546
*[0-9]* instructions per context switch
4647
. voluntary context switches
4748
0 direct context switches
49+
0 context switch sequence injections
4850
100\.00% voluntary switches
4951
0\.00% direct switches
5052
.*
@@ -56,6 +58,7 @@ Core #1 counts:
5658
*[0-9]* instructions per context switch
5759
. voluntary context switches
5860
0 direct context switches
61+
0 context switch sequence injections
5962
100\.00% voluntary switches
6063
0\.00% direct switches
6164
.*
@@ -67,6 +70,7 @@ Core #2 counts:
6770
*[0-9]* instructions per context switch
6871
. voluntary context switches
6972
0 direct context switches
73+
0 context switch sequence injections
7074
100\.00% voluntary switches
7175
0\.00% direct switches
7276
.*
@@ -78,6 +82,7 @@ Core #3 counts:
7882
*[0-9]* instructions per context switch
7983
. voluntary context switches
8084
0 direct context switches
85+
0 context switch sequence injections
8186
100\.00% voluntary switches
8287
0\.00% direct switches
8388
.*

‎clients/drcachesim/tests/switch_insertion.templatex‎

Lines changed: 26 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,28 @@
1-
Basic counts tool results:
1+
Schedule stats tool results:
22
Total counts:
3-
[1-9][0-9][0-9][0-9][0-9][0-9] total \(fetched\) instructions
4-
5971 total unique \(fetched\) instructions
5-
[1-9][0-9][0-9][0-9][0-9][0-9] total userspace instructions
6-
[1-9][0-9][0-9] total kernel instructions
7-
[1-9][0-9][0-9][0-9][0-9][0-9] total non-fetched instructions
3+
4 cores
4+
.*
5+
639664 instructions
6+
11 total context switches
7+
.*
8+
6 voluntary context switches
9+
0 direct context switches
10+
363 context switch sequence injections
11+
.*
12+
9 switches input-to-input
13+
5 switches input-to-idle
14+
2 switches idle-to-input
15+
.*
16+
Core #0 counts:
17+
.*
18+
117223 instructions
19+
8 total context switches
20+
.*
21+
3 voluntary context switches
22+
0 direct context switches
23+
104 context switch sequence injections
24+
.*
25+
6 switches input-to-input
26+
3 switches input-to-idle
27+
2 switches idle-to-input
828
.*

‎clients/drcachesim/tools/schedule_stats.cpp‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/* **********************************************************
2-
* Copyright (c) 2017-2024 Google, Inc. All rights reserved.
2+
* Copyright (c) 2017-2025 Google, Inc. All rights reserved.
33
* **********************************************************/
44

55
/*
@@ -166,6 +166,9 @@ schedule_stats_t::get_scheduler_stats(memtrace_stream_t *stream, counters_t &cou
166166
memtrace_stream_t::SCHED_STAT_RUNQUEUE_REBALANCES));
167167
counters.at_output_limit = static_cast<int64_t>(
168168
stream->get_schedule_statistic(memtrace_stream_t::SCHED_STAT_HIT_OUTPUT_LIMIT));
169+
counters.switch_sequence_injections =
170+
static_cast<int64_t>(stream->get_schedule_statistic(
171+
memtrace_stream_t::SCHED_STAT_KERNEL_SWITCH_SEQUENCE_INJECTIONS));
169172

170173
// XXX: Currently, schedule_stats is measuring swap-ins to a real input. If we
171174
// want to match what "perf" targeting this app would record, which is swap-outs,
@@ -420,6 +423,8 @@ schedule_stats_t::print_counters(const counters_t &counters)
420423
<< counters.voluntary_switches << " voluntary context switches\n";
421424
std::cerr << std::setw(12) << counters.direct_switches
422425
<< " direct context switches\n";
426+
std::cerr << std::setw(12) << counters.switch_sequence_injections
427+
<< " context switch sequence injections\n";
423428
print_percentage(static_cast<double>(counters.voluntary_switches),
424429
static_cast<double>(counters.total_switches),
425430
"% voluntary switches\n");

‎clients/drcachesim/tools/schedule_stats.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/* **********************************************************
2-
* Copyright (c) 2023-2024 Google, Inc. All rights reserved.
2+
* Copyright (c) 2023-2025 Google, Inc. All rights reserved.
33
* **********************************************************/
44

55
/*
@@ -216,6 +216,7 @@ class schedule_stats_t : public analysis_tool_t {
216216
syscalls += rhs.syscalls;
217217
maybe_blocking_syscalls += rhs.maybe_blocking_syscalls;
218218
direct_switch_requests += rhs.direct_switch_requests;
219+
switch_sequence_injections += rhs.switch_sequence_injections;
219220
observed_migrations += rhs.observed_migrations;
220221
waits += rhs.waits;
221222
idles += rhs.idles;
@@ -252,6 +253,7 @@ class schedule_stats_t : public analysis_tool_t {
252253
int64_t syscalls = 0;
253254
int64_t maybe_blocking_syscalls = 0;
254255
int64_t direct_switch_requests = 0;
256+
int64_t switch_sequence_injections = 0;
255257
// Our observed migrations will be <= the scheduler's reported migrations
256258
// for a dynamic schedule as we don't know the initial runqueue allocation
257259
// and so can't see the migration of an input that didn't execute in the

‎suite/tests/CMakeLists.txt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4067,7 +4067,7 @@ if (BUILD_CLIENTS)
40674067
set(switch_file
40684068
"${PROJECT_SOURCE_DIR}/clients/drcachesim/tests/mock_switch_sequences.x64.zip")
40694069
torunonly_simtool(switch_insertion ${ci_shared_app}
4070-
"-indir ${thread_trace_dir} -tool basic_counts -core_sharded -sched_quantum 1000 -sched_switch_file ${switch_file}"
4070+
"-indir ${thread_trace_dir} -tool schedule_stats -core_sharded -sched_quantum 1000 -sched_switch_file ${switch_file}"
40714071
"")
40724072
set(tool.switch_insertion_rawtemp ON) # no preprocessor
40734073

0 commit comments

Comments
 (0)