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insert_reachable_cti: on arm32, use the lower order bit in the given … #2457

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insert_reachable_cti: on arm32, use the lower order bit in the given … #2457

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insert_reachable_cti: on arm32, use the lower order bit in the given …
aleden May 31, 2017
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Merge branch 'master' into master
fhahn Mar 23, 2018
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Merge branch 'master' into master
fhahn Mar 27, 2018
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3 changes: 1 addition & 2 deletions core/arch/aarchxx/mangle.c
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Expand Up @@ -986,8 +986,7 @@ insert_reachable_cti(dcontext_t *dcontext, instrlist_t *ilist, instr_t *where,
{
ASSERT(scratch != REG_NULL); /* required */
/* load target into scratch register */
insert_mov_immed_ptrsz(dcontext, (ptr_int_t)
PC_AS_JMP_TGT(dr_get_isa_mode(dcontext), target),

@derekbruening derekbruening Jun 1, 2017

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What I'm puzzling over is the reason that 850c10c put this here: it is called out in the commit message so there must have been something that did not have the lsb set. Not everything does: e.g., fragment tags deliberately do not have lsb set. There must have been something like that that would make its way here. Does a test suite run on arm hit any discrepancy here?

@fhahn fhahn Mar 23, 2018

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I think for clean calls, we can rely on the ARM/Thumb bit being set properly in the address of the function. But I am not sure if that is true for the code DynamoRIO emits itself? Then we would need to set it explicitly when moving the address to a register.

insert_mov_immed_ptrsz(dcontext, (ptr_int_t)target,
opnd_create_reg(scratch), ilist, where, NULL, NULL);
/* even if a call and not a jmp, we can skip this if it doesn't return */
if (!jmp && returns) {
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