💚 fix c28x initial state issues according to TI docs

Author: EDI-Systems

Include/Platform/C28X/Chip/TMS320F2812/rmp_platform_tms320f2812.h

@@ -54,6 +54,7 @@ do \
     InitSysCtrl(); \
     /* Initialize vector table and sources but not global interrupt yet */ \
     InitPieVectTable(); \
+    IFR=0x0000U; \
     IER=0xFFFFU; \
     /* Initialize RAMFUNC */ \
     MemCopy(&RamfuncsLoadStart,&RamfuncsLoadEnd,&RamfuncsRunStart); \

Include/Platform/C28X/Chip/TMS320F28335/rmp_platform_tms320f28335.h

@@ -54,6 +54,7 @@ do \
     InitSysCtrl(); \
     /* Initialize vector table and sources but not global interrupt yet */ \
     InitPieVectTable(); \
+    IFR=0x0000U; \
     IER=0xFFFFU; \
     /* Initialize RAMFUNC */ \
     MemCopy(&RamfuncsLoadStart,&RamfuncsLoadEnd,&RamfuncsRunStart); \

Include/Platform/C28X/rmp_platform_c28x_ticc.inc

@@ -51,6 +51,8 @@ RMP_C28X_SWITCH_PRE         .macro
     MOV                     DP,#__RMP_C28X_SP_Kern
     MOV                     AL,@__RMP_C28X_SP_Kern
     MOV                     SP,AL
+    SPM                     0
+    CLRC                    OVM
     .endm
 
 ;/* Finish up the context switch **********************************************/

Include/Test/Chip/rmp_test_tms320f2812.h

@@ -62,12 +62,13 @@ Return      : None.
 ******************************************************************************/
 void Timer_Init(void)
 {
+    CpuTimer1Regs.TCR.bit.TIE=0U;
     CpuTimer1Regs.TCR.bit.TSS=1U;
+    CpuTimer1Regs.TCR.bit.TIF=0U;
     CpuTimer1Regs.PRD.all=0xFFFFU;
     CpuTimer1Regs.TPR.all=0U;
     CpuTimer1Regs.TPRH.all=0U;
     CpuTimer1Regs.TCR.bit.TRB=1U;
-    CpuTimer1Regs.TCR.bit.TIE=0U;
     CpuTimer1Regs.TCR.bit.TSS=0U;
 }
 /* End Function:Timer_Init ***************************************************/

Include/Test/Chip/rmp_test_tms320f28335.h

@@ -117,12 +117,13 @@ Return      : None.
 ******************************************************************************/
 void Timer_Init(void)
 {
+    CpuTimer1Regs.TCR.bit.TIE=0U;
     CpuTimer1Regs.TCR.bit.TSS=1U;
+    CpuTimer1Regs.TCR.bit.TIF=0U;
     CpuTimer1Regs.PRD.all=0xFFFFU;
     CpuTimer1Regs.TPR.all=0U;
     CpuTimer1Regs.TPRH.all=0U;
     CpuTimer1Regs.TCR.bit.TRB=1U;
-    CpuTimer1Regs.TCR.bit.TIE=0U;
     CpuTimer1Regs.TCR.bit.TSS=0U;
 }
 /* End Function:Timer_Init ***************************************************/

Source/Platform/C28X/rmp_platform_c28x.c

@@ -51,7 +51,9 @@ rmp_ptr_t _RMP_Stack_Init(rmp_ptr_t Stack,
     Ctx->PC=Entry;
     Ctx->ACC=Param;
 
-    /* No product shift, sign extend, aux ptr 0, interrupt enabled upon entry */
+    /* No product shift (SPM 0/PM=3'b001), sign extend enabled (SXM=1), no
+     * saturation (OVM=0), aux ptr 0 (ARP=0), interrupt enabled (INTM=0),
+     * no C27x compatibility mode (PAGE0=0) upon thread entry */
     Ctx->T_ST0=0x00000081U;
     Ctx->DP_ST1=0x00000A08U;
 

Source/Platform/C28X/rmp_platform_c28x_ticc.s

@@ -138,7 +138,7 @@ RMP_C28X_SAVE               .macro LABEL
     POP                     ACC
     AND                     AL,#0xFFFEU
     PUSH                    ACC
-    ;Push 0 for DBGSTAT; clear emulation context
+    ;Push 0 for DBGSTAT, may mess debugging up but we have no choice
     XOR                     AH,AH
     MOV                     AL,IER
     PUSH                    ACC
@@ -169,6 +169,12 @@ RMP_C28X_SWITCH             .macro
     MOV                     DP,#__RMP_C28X_SP_Kern
     MOV                     AH,@__RMP_C28X_SP_Kern
     MOV                     SP,AH
+    ;C runtime assumes SPM 0 (PM=3'b001), OVM=0 and PAGE0=0, but PAGE0 is always
+    ;0 for C28x, and this yield stub is masqueraded as a C function. As a result,
+    ;we don't need to set anything here, because the compiler must have done that
+    ;for us. However, we have to SPM 0 and CLRC OVM at the interrupt because we
+    ;have no clue when an interrupt will kick in. We don't need to ASP/NASP
+    ;there because we're using a separate kernel stack to run the kernel code.
     LCR                     __RMP_Run_High
     MOV                     DP,#_RMP_SP_Cur
     MOV                     AH,@_RMP_SP_Cur