removing tracking of oas, pnl, sdf, update doc

Author: Essenceia

Makefile

@@ -26,7 +26,7 @@ GATE_PHONY_LIB:= lib
 IMPLEM_DIR := final
 SUBMIT_PATH:=$(IMPLEM_DIR)/analog_submission
 
-.PHONY: firmware openocd gdb fpga fpga_prog lint lint_fpga lint_gate_phony tv test gates sdf def gl sc_extract submit
+.PHONY: firmware openocd gdb fpga fpga_prog lint lint_fpga lint_gate_phony tv test gates def gl sc_extract submit
 
 ########
 # Lint #
@@ -86,9 +86,6 @@ LIBRELANE_FINAL:=$(strip $(shell find $(LIBRELANE_RUN_PATH) -type d -name final
 ifneq ($(LIBRELANE_FINAL),)
 gates:
 	cp $(LIBRELANE_FINAL)/nl/$(PROJET_NAME).nl.v $(IMPLEM_DIR)/.
-	cp $(LIBRELANE_FINAL)/pnl/$(PROJET_NAME).pnl.v $(IMPLEM_DIR)/.
-sdf:
-	cp $(LIBRELANE_FINAL)/sdf/nom_typ_1p20V_25C/* $(IMPLEM_DIR)/.
 def:
 	cp $(LIBRELANE_FINAL)/def/$(PROJET_NAME).def $(IMPLEM_DIR)/.
 else

docs/info.md

@@ -33,7 +33,7 @@ This accelerator uses the following pinout:
 
 This MAC accelerator operates at up to 100MHz and is capable of reaching up to 100 MMAC/s or 200 MFLOPS/s. 
 
-:warning: The outgoing data path on IHP sg13g2 chips has only been proven upwards of 75MHz, so although we will using the maximum theoretical frequency in this discussion it might be necessary to drive this ASIC as a lower clock frequency in practice. 
+:warning: The outgoing data path on IHP sg13g2 chips has only been proven upwards of 75MHz, so although we will using the maximum theoretical frequency in this discussion in practive we will be necessary to drive this ASIC as a lower clock frequency in practice. 
 
 ## Background