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instcountci: Implement x87 invalid operation bit on F64 mode
1 parent cb91e1d commit 108a199

49 files changed

Lines changed: 39385 additions & 1678 deletions

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‎unittests/InstructionCountCI/AFP/H0F3A.json‎

Lines changed: 40 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -11,102 +11,132 @@
1111
},
1212
"Instructions": {
1313
"roundss xmm0, xmm1, 00000000b": {
14-
"ExpectedInstructionCount": 1,
14+
"ExpectedInstructionCount": 4,
1515
"Comment": [
1616
"Nearest rounding",
1717
"0x66 0x0f 0x3a 0x0a"
1818
],
1919
"ExpectedArm64ASM": [
20+
"mrs x0, S3_3_c4_c4_1",
21+
"and w0, w0, #0xfffffffe",
22+
"msr S3_3_c4_c4_1, x0",
2023
"frintn s16, s17"
2124
]
2225
},
2326
"roundss xmm0, xmm1, 00000001b": {
24-
"ExpectedInstructionCount": 1,
27+
"ExpectedInstructionCount": 4,
2528
"Comment": [
2629
"-inf rounding",
2730
"0x66 0x0f 0x3a 0x0a"
2831
],
2932
"ExpectedArm64ASM": [
33+
"mrs x0, S3_3_c4_c4_1",
34+
"and w0, w0, #0xfffffffe",
35+
"msr S3_3_c4_c4_1, x0",
3036
"frintm s16, s17"
3137
]
3238
},
3339
"roundss xmm0, xmm1, 00000010b": {
34-
"ExpectedInstructionCount": 1,
40+
"ExpectedInstructionCount": 4,
3541
"Comment": [
3642
"+inf rounding",
3743
"0x66 0x0f 0x3a 0x0a"
3844
],
3945
"ExpectedArm64ASM": [
46+
"mrs x0, S3_3_c4_c4_1",
47+
"and w0, w0, #0xfffffffe",
48+
"msr S3_3_c4_c4_1, x0",
4049
"frintp s16, s17"
4150
]
4251
},
4352
"roundss xmm0, xmm1, 00000011b": {
44-
"ExpectedInstructionCount": 1,
53+
"ExpectedInstructionCount": 4,
4554
"Comment": [
4655
"truncate rounding",
4756
"0x66 0x0f 0x3a 0x0a"
4857
],
4958
"ExpectedArm64ASM": [
59+
"mrs x0, S3_3_c4_c4_1",
60+
"and w0, w0, #0xfffffffe",
61+
"msr S3_3_c4_c4_1, x0",
5062
"frintz s16, s17"
5163
]
5264
},
5365
"roundss xmm0, xmm1, 00000100b": {
54-
"ExpectedInstructionCount": 1,
66+
"ExpectedInstructionCount": 4,
5567
"Comment": [
5668
"host rounding mode rounding",
5769
"0x66 0x0f 0x3a 0x0a"
5870
],
5971
"ExpectedArm64ASM": [
72+
"mrs x0, S3_3_c4_c4_1",
73+
"and w0, w0, #0xfffffffe",
74+
"msr S3_3_c4_c4_1, x0",
6075
"frinti s16, s17"
6176
]
6277
},
6378
"roundsd xmm0, xmm1, 00000000b": {
64-
"ExpectedInstructionCount": 1,
79+
"ExpectedInstructionCount": 4,
6580
"Comment": [
6681
"Nearest rounding",
6782
"0x66 0x0f 0x3a 0x0b"
6883
],
6984
"ExpectedArm64ASM": [
85+
"mrs x0, S3_3_c4_c4_1",
86+
"and w0, w0, #0xfffffffe",
87+
"msr S3_3_c4_c4_1, x0",
7088
"frintn d16, d17"
7189
]
7290
},
7391
"roundsd xmm0, xmm1, 00000001b": {
74-
"ExpectedInstructionCount": 1,
92+
"ExpectedInstructionCount": 4,
7593
"Comment": [
7694
"-inf rounding",
7795
"0x66 0x0f 0x3a 0x0b"
7896
],
7997
"ExpectedArm64ASM": [
98+
"mrs x0, S3_3_c4_c4_1",
99+
"and w0, w0, #0xfffffffe",
100+
"msr S3_3_c4_c4_1, x0",
80101
"frintm d16, d17"
81102
]
82103
},
83104
"roundsd xmm0, xmm1, 00000010b": {
84-
"ExpectedInstructionCount": 1,
105+
"ExpectedInstructionCount": 4,
85106
"Comment": [
86107
"+inf rounding",
87108
"0x66 0x0f 0x3a 0x0b"
88109
],
89110
"ExpectedArm64ASM": [
111+
"mrs x0, S3_3_c4_c4_1",
112+
"and w0, w0, #0xfffffffe",
113+
"msr S3_3_c4_c4_1, x0",
90114
"frintp d16, d17"
91115
]
92116
},
93117
"roundsd xmm0, xmm1, 00000011b": {
94-
"ExpectedInstructionCount": 1,
118+
"ExpectedInstructionCount": 4,
95119
"Comment": [
96120
"truncate rounding",
97121
"0x66 0x0f 0x3a 0x0b"
98122
],
99123
"ExpectedArm64ASM": [
124+
"mrs x0, S3_3_c4_c4_1",
125+
"and w0, w0, #0xfffffffe",
126+
"msr S3_3_c4_c4_1, x0",
100127
"frintz d16, d17"
101128
]
102129
},
103130
"roundsd xmm0, xmm1, 00000100b": {
104-
"ExpectedInstructionCount": 1,
131+
"ExpectedInstructionCount": 4,
105132
"Comment": [
106133
"host rounding mode rounding",
107134
"0x66 0x0f 0x3a 0x0b"
108135
],
109136
"ExpectedArm64ASM": [
137+
"mrs x0, S3_3_c4_c4_1",
138+
"and w0, w0, #0xfffffffe",
139+
"msr S3_3_c4_c4_1, x0",
110140
"frinti d16, d17"
111141
]
112142
}

‎unittests/InstructionCountCI/AFP/SVE256/Secondary.json‎

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,19 +10,22 @@
1010
},
1111
"Instructions": {
1212
"cvtpi2ps xmm0, [rax]": {
13-
"ExpectedInstructionCount": 4,
13+
"ExpectedInstructionCount": 7,
1414
"Comment": [
1515
"0x0f 0x2a"
1616
],
1717
"ExpectedArm64ASM": [
1818
"ldr d2, [x4]",
19+
"mrs x0, S3_3_c4_c4_1",
20+
"and w0, w0, #0xfffffffe",
21+
"msr S3_3_c4_c4_1, x0",
1922
"scvtf v0.2s, v2.2s",
2023
"ptrue p0.d, vl1",
2124
"mov z16.d, p0/m, z0.d"
2225
]
2326
},
2427
"cvtpi2ps xmm0, mm0": {
25-
"ExpectedInstructionCount": 7,
28+
"ExpectedInstructionCount": 10,
2629
"Comment": [
2730
"0x0f 0x2a"
2831
],
@@ -31,6 +34,9 @@
3134
"mov w20, #0xffff",
3235
"strb w20, [x28, #1186]",
3336
"ldr d2, [x28, #1040]",
37+
"mrs x0, S3_3_c4_c4_1",
38+
"and w0, w0, #0xfffffffe",
39+
"msr S3_3_c4_c4_1, x0",
3440
"scvtf v0.2s, v2.2s",
3541
"ptrue p0.d, vl1",
3642
"mov z16.d, p0/m, z0.d"

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