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asm_tests: Implement x87 invalid operation bit on F64 mode
1 parent 42b1891 commit fecf6ba

19 files changed

Lines changed: 554 additions & 0 deletions

‎unittests/ASM/X87_F64/cumulative_ioc_test_F64.asm‎

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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "0",
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"RBX": "1"
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},
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"Env": { "FEX_X87REDUCEDPRECISION" : "1" }
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}
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%endif
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; We do one an invalid operation, then a valid one.
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; The bit should be set correctly after the invalid operation,
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; and cleared by the valid operation.
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fldz
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fldz
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fdiv ; division by zero.
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fstsw ax
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mov bx, ax
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and bx, 1
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fld1
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fld1
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fadd ; valid operation
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fstsw ax
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and ax, 1
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hlt

‎unittests/ASM/X87_F64/invalid_div_zero_F64.asm‎

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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "1"
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},
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"Env": { "FEX_X87REDUCEDPRECISION" : "1" }
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}
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%endif
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; Test 0/0 = Invalid Operation (should set bit 0 of status word) - reduced precision
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fldz
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fldz
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fdiv
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fstsw ax
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and rax, 1
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hlt

‎unittests/ASM/X87_F64/invalid_fcos_infinity_F64.asm‎

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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "1"
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}
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}
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%endif
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; Test fcos(+infinity) in reduced precision mode = Invalid Operation (should set bit 0 of status word)
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finit
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; Set reduced precision mode (64-bit)
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fnstcw [rel .cw]
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mov ax, [rel .cw]
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and ax, 0xFCFF ; Clear precision bits (bits 8-9)
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or ax, 0x0200 ; Set to 64-bit precision (10b)
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mov [rel .cw], ax
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fldcw [rel .cw]
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; Load positive infinity: IEEE 754 double precision infinity
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mov rax, 0x7FF0000000000000
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mov [rel .pos_inf], rax
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fld qword [rel .pos_inf]
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fcos
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fstsw ax
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and rax, 1
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hlt
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.cw:
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dw 0
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.pos_inf:
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dq 0

‎unittests/ASM/X87_F64/invalid_fist_nan_F64.asm‎

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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "1",
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"RBX": "1"
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},
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"Env": { "FEX_X87REDUCEDPRECISION" : "1" }
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}
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%endif
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section .data
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.dummy: dq 0x0
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section .text
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global _start
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_start:
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; Test FIST with NaN = Invalid Operation (should set bit 0 of status word) - reduced precision
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; Create NaN by 0/0
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fldz
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fldz
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fdiv
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fstsw ax
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and rax, 1
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mov rbx, rax
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; Try to convert NaN to integer - this should be invalid
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fistp dword [rel .dummy]
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fstsw ax
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and rax, 1
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hlt

‎unittests/ASM/X87_F64/invalid_fist_overflow_16bit_F64.asm‎

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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "1"
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},
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"Env": { "FEX_X87REDUCEDPRECISION" : "1" }
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}
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%endif
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section .rodata
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.thirty: dq 30
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section .bss
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.dummy: resw 1
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section .text
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global _start
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_start:
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; Test FIST with 16-bit overflow = Invalid Operation (should set bit 0 of status word) - reduced precision
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; Create a large number that will overflow int16
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; Load 2^20 (larger than int16 range: max int16 = 32767, 2^20 = 1048576)
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finit
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fild dword [rel .thirty]
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fld1
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fscale
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; Try to convert to int16 - this should overflow and be invalid
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fistp word [rel .dummy]
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fstsw ax
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and rax, 1
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hlt

‎unittests/ASM/X87_F64/invalid_fist_overflow_F64.asm‎

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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "1"
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},
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"Env": { "FEX_X87REDUCEDPRECISION" : "1" }
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}
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%endif
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section .rodata
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.fifty: dq 50
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section .bss
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.dummy: resb 4
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section .text
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global _start
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_start:
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; Test FIST with overflow = Invalid Operation (should set bit 0 of status word) - reduced precision
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; Create a very large number that will overflow int32
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; Load 2^32 (larger than int32 range)
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finit
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fild dword [rel .fifty]
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fld1
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fscale
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; Try to convert to int32 - this should overflow and be invalid
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fistp dword [rel .dummy]
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fstsw ax
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and rax, 1
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hlt

‎unittests/ASM/X87_F64/invalid_fprem_infinity_F64.asm‎

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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "1"
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},
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"Env": { "FEX_X87REDUCEDPRECISION" : "1" }
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}
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%endif
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; Test FPREM with simple operands - reduced precision
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finit
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; Load simple operands: fprem(1.0, 0.0) should set Invalid Operation
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fldz
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fld1
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; Do FPREM: ST(0) = fprem(ST(0), ST(1)) = fprem(1.0, 0.0)
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; fprem(1.0, 0.0) should set Invalid Operation because divisor is zero
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fprem
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fstsw ax
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and rax, 1
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hlt

‎unittests/ASM/X87_F64/invalid_fptan_infinity_F64.asm‎

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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "1"
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}
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}
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%endif
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; Test fptan(+infinity) in reduced precision mode = Invalid Operation (should set bit 0 of status word)
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finit
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; Set reduced precision mode (64-bit)
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fnstcw [rel .cw]
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mov ax, [rel .cw]
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and ax, 0xFCFF ; Clear precision bits (bits 8-9)
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or ax, 0x0200 ; Set to 64-bit precision (10b)
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mov [rel .cw], ax
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fldcw [rel .cw]
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; Load positive infinity: IEEE 754 double precision infinity
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mov rax, 0x7FF0000000000000
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mov [rel .pos_inf], rax
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fld qword [rel .pos_inf]
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fptan
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fstsw ax
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and rax, 1
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hlt
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.cw:
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dw 0
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.pos_inf:
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dq 0

‎unittests/ASM/X87_F64/invalid_fsin_infinity_F64.asm‎

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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "1"
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}
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}
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%endif
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; Test fsin(+infinity) in reduced precision mode = Invalid Operation (should set bit 0 of status word)
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finit
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; Set reduced precision mode (64-bit)
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fnstcw [rel .cw]
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mov ax, [rel .cw]
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and ax, 0xFCFF ; Clear precision bits (bits 8-9)
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or ax, 0x0200 ; Set to 64-bit precision (10b)
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mov [rel .cw], ax
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fldcw [rel .cw]
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; Load positive infinity: IEEE 754 double precision infinity
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mov rax, 0x7FF0000000000000
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mov [rel .pos_inf], rax
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fld qword [rel .pos_inf]
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fsin
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fstsw ax
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and rax, 1
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hlt
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.cw:
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dw 0
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.pos_inf:
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dq 0

‎unittests/ASM/X87_F64/invalid_fsincos_infinity_F64.asm‎

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%ifdef CONFIG
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{
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"RegData": {
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"RAX": "1"
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}
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}
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%endif
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; Test fsincos(+infinity) in reduced precision mode = Invalid Operation (should set bit 0 of status word)
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finit
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; Set reduced precision mode (64-bit)
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fnstcw [rel .cw]
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mov ax, [rel .cw]
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and ax, 0xFCFF ; Clear precision bits (bits 8-9)
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or ax, 0x0200 ; Set to 64-bit precision (10b)
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mov [rel .cw], ax
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fldcw [rel .cw]
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; Load positive infinity: IEEE 754 double precision infinity
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mov rax, 0x7FF0000000000000
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mov [rel .pos_inf], rax
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fld qword [rel .pos_inf]
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fsincos
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fstsw ax
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and rax, 1
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hlt
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.cw:
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dw 0
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.pos_inf:
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dq 0

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