With the ADC left aligned:

diff --git a/processing.cpp b/processing.cpp
index 85babfa..e4bffcb 100644
--- a/processing.cpp
+++ b/processing.cpp
@@ -18,14 +18,11 @@
 #include "utils_pins.h"
 #include "shared_var.h"
 
-// Define operating limits for the LP filters which identify DC offset in the voltage
-// sample streams. By limiting the output range, these filters always should start up
-// correctly.
-constexpr int32_t l_DCoffset_V_min{ (512L - 100L) * 256L }; /**< mid-point of ADC minus a working margin */
-constexpr int32_t l_DCoffset_V_max{ (512L + 100L) * 256L }; /**< mid-point of ADC plus a working margin */
-constexpr int16_t i_DCoffset_I_nom{ 512L };                 /**< nominal mid-point value of ADC @ x1 scale */
 
-int32_t l_DCoffset_V[NO_OF_PHASES]{}; /**< <--- for LPF */
+// Define ideal bias, ADC mid-range, left aligned.
+constexpr uint16_t i_DCoffset_V_nom{ 511U << 6 };  /**< nominal mid-point value of ADC @ x64 scale */
+
+uint16_t i_DCoffset_V[NO_OF_PHASES]{}; /**< <--- for LPF */
 
 /**< main energy bucket for 3-phase use, with units of Joules * SUPPLY_FREQUENCY */
 constexpr float f_capacityOfEnergyBucket_main{ static_cast< float >(WORKING_ZONE_IN_JOULES * SUPPLY_FREQUENCY) };
@@ -66,8 +63,8 @@ constexpr uint8_t POST_TRANSITION_MAX_COUNT{ 3 }; /**< allows each transition to
 uint8_t activeLoad{ NO_OF_DUMPLOADS }; /**< current active load */
 
 int32_t l_sumP[NO_OF_PHASES]{};                /**< cumulative power per phase */
-int32_t l_sampleVminusDC[NO_OF_PHASES]{};      /**< current raw voltage sample filtered */
-int32_t l_cumVdeltasThisCycle[NO_OF_PHASES]{}; /**< for the LPF which determines DC offset (voltage) */
+int16_t i_sampleVminusDC[NO_OF_PHASES]{};      /**< current raw voltage sample filtered */
+uint32_t l_filterDC_V[NO_OF_PHASES]{};         /**< for the LPF which determines DC offset (voltage) */
 int32_t l_sumP_atSupplyPoint[NO_OF_PHASES]{};  /**< for summation of 'real power' values during datalog period */
 int32_t l_sum_Vsquared[NO_OF_PHASES]{};        /**< for summation of V^2 values during datalog period */
 
@@ -108,13 +105,13 @@ bool beyondStartUpPeriod{ false }; /**< start-up delay, allows things to settle
  *
  * @ingroup Initialization
  */
-template< size_t N >
-constexpr void initializeArray(int32_t (&array)[N], int32_t value)
+template<typename T, size_t N>
+constexpr void initializeArray(T (&array)[N], T value)
 {
-  for (size_t i = 0; i < N; ++i)
-  {
-    array[i] = value;
-  }
+    for (size_t i = 0; i < N; ++i)
+    {
+        array[i] = value;
+    }
 }
 
 /**
@@ -241,7 +238,10 @@ constexpr uint16_t getInputPins()
  */
 void initializeProcessing()
 {
-  initializeArray(l_DCoffset_V, 512L * 256L);  // nominal mid-point value of ADC @ x256 scale
+  initializeArray(i_DCoffset_V, i_DCoffset_V_nom);  // nominal mid-point value of ADC left-aligned, x64 scale
+
+  constexpr uint32_t filterDC_V_nom = static_cast<uint32_t>(i_DCoffset_V_nom) << 15;
+  initializeArray(l_filterDC_V, filterDC_V_nom);  // nominal mid-point value of ADC left-aligned
 
   setPinsAsOutput(getOutputPins());      // set the output pins as OUTPUT
   setPinsAsInputPullup(getInputPins());  // set the input pins as INPUT_PULLUP
@@ -397,12 +397,13 @@ void updatePhysicalLoadStates()
  *
  * @ingroup TimeCritical
  */
-void processPolarity(const uint8_t phase, const int16_t rawSample)
+void processPolarity(const uint8_t phase, const uint16_t rawSample)
 {
   // remove DC offset from each raw voltage sample by subtracting the accurate value
   // as determined by its associated LP filter.
-  l_sampleVminusDC[phase] = (static_cast< int32_t >(rawSample) << 8) - l_DCoffset_V[phase];
-  polarityOfMostRecentSampleV[phase] = (l_sampleVminusDC[phase] > 0) ? Polarities::POSITIVE : Polarities::NEGATIVE;
+  // Add 0.5 for the rounding, +32 when 10-bits left aligned `1<<(15-10)`
+  i_sampleVminusDC[phase] = (rawSample | 32U) - i_DCoffset_V[phase];  // +0.5 for the rounding
+  polarityOfMostRecentSampleV[phase] = (i_sampleVminusDC[phase] > 0) ? Polarities::POSITIVE : Polarities::NEGATIVE;
 }
 
 /**
@@ -422,24 +423,30 @@ void processPolarity(const uint8_t phase, const int16_t rawSample)
  *
  * @ingroup TimeCritical
  */
-void processCurrentRawSample(const uint8_t phase, const int16_t rawSample)
+void processCurrentRawSample(const uint8_t phase, const uint16_t rawSample)
 {
   // extra items for an LPF to improve the processing of data samples from CT1
   static int32_t lpf_long[NO_OF_PHASES]{};  // new LPF, for offsetting the behaviour of CTx as a HPF
 
-  // remove most of the DC offset from the current sample (the precise value does not matter)
-  int32_t sampleIminusDC = (static_cast< int32_t >(rawSample - i_DCoffset_I_nom)) << 8;
+  // remove most of the DC offset from the current sample.
+  // Use the voltage bias, it's most likely more accurate than the default mid-range.
+  // Add 0.5 for the rounding, +32 when 10-bits left aligned `1<<(15-10)`
+  int16_t sampleIminusDC = (rawSample | 32U) - i_DCoffset_V[phase];
 
   // extra filtering to offset the HPF effect of CTx
-  const int32_t last_lpf_long{ lpf_long[phase] };
-  lpf_long[phase] += alpha * (sampleIminusDC - last_lpf_long);
-  sampleIminusDC += (lpf_gain * lpf_long[phase]);
+  if (lpf_gain != 0.0F && alpha != 0.0F)
+  {
+    const int32_t last_lpf_long{ lpf_long[phase] };
+    lpf_long[phase] += alpha * (sampleIminusDC - last_lpf_long);
+    sampleIminusDC += (lpf_gain * lpf_long[phase]);
+  }
 
   // calculate the "real power" in this sample pair and add to the accumulated sum
-  const int32_t filtV_div4 = l_sampleVminusDC[phase] >> 2;  // reduce to 16-bits (now x64, or 2^6)
-  const int32_t filtI_div4 = sampleIminusDC >> 2;           // reduce to 16-bits (now x64, or 2^6)
+  const int32_t filtV_div4 = i_sampleVminusDC[phase];  // 16-bits left aligned (x64, or 2^6)
+  const int32_t filtI_div4 = sampleIminusDC;           // 16-bits left aligned (x64, or 2^6)
   int32_t instP = filtV_div4 * filtI_div4;                  // 32-bits (now x4096, or 2^12)
   instP >>= 12;                                             // scaling is now x1, as for Mk2 (V_ADC x I_ADC)
+  // TODO: optimization, scale to x4 (instP >>= 8) to avoid multiple shifts
 
   l_sumP[phase] += instP;                // cumulative power, scaling as for Mk2 (V_ADC x I_ADC)
   l_sumP_atSupplyPoint[phase] += instP;  // cumulative power, scaling as for Mk2 (V_ADC x I_ADC)
@@ -498,8 +505,8 @@ void confirmPolarity(const uint8_t phase)
 void processVoltage(const uint8_t phase)
 {
   // for the Vrms calculation (for datalogging only)
-  const int32_t filtV_div4{ l_sampleVminusDC[phase] >> 2 };  // reduce to 16-bits (now x64, or 2^6)
-  int32_t inst_Vsquared{ filtV_div4 * filtV_div4 };          // 32-bits (now x4096, or 2^12)
+  const int32_t filtV_div4{ i_sampleVminusDC[phase] };  // 16-bits left aligned (x64, or 2^6)
+  int32_t inst_Vsquared{ filtV_div4 * filtV_div4 };  // 32-bits left aligned (now x4096, or 2^12)
 
   if constexpr (DATALOG_PERIOD_IN_SECONDS > 10)
   {
@@ -508,12 +515,13 @@ void processVoltage(const uint8_t phase)
   else
   {
     inst_Vsquared >>= 12;  // scaling is now x1 (V_ADC x I_ADC)
+    // TODO: optimization, scale to x4 (inst_Vsquared >>= 8) to avoid multiple shifts
   }
 
   l_sum_Vsquared[phase] += inst_Vsquared;  // cumulative V^2 (V_ADC x I_ADC)
   //
   // store items for use during next loop
-  l_cumVdeltasThisCycle[phase] += l_sampleVminusDC[phase];           // for use with LP filter
+  l_filterDC_V[phase] += i_sampleVminusDC[phase];                    // for use with LP filter
   polarityConfirmedOfLastSampleV[phase] = polarityConfirmed[phase];  // for identification of half cycle boundaries
   ++n_samplesDuringThisMainsCycle[phase];                            // for real power calculations
 }
@@ -742,24 +750,19 @@ void processMinusHalfCycle(const uint8_t phase)
 {
   // This is a convenient point to update the Low Pass Filter for removing the DC
   // component from the phase that is being processed.
-  // The portion which is fed back into the integrator is approximately one percent
-  // of the average offset of all the SampleVs in the previous mains cycle.
-  //
-  l_DCoffset_V[phase] += (l_cumVdeltasThisCycle[phase] >> 12);
-  l_cumVdeltasThisCycle[phase] = 0;
+  i_DCoffset_V[phase] = l_filterDC_V[phase] >> 15;
 
-  // To ensure that this LP filter will always start up correctly when 240V AC is
-  // available, its output value needs to be prevented from drifting beyond the likely range
-  // of the voltage signal.
-  //
-  if (l_DCoffset_V[phase] < l_DCoffset_V_min)
-  {
-    l_DCoffset_V[phase] = l_DCoffset_V_min;
-  }
-  else if (l_DCoffset_V[phase] > l_DCoffset_V_max)
-  {
-    l_DCoffset_V[phase] = l_DCoffset_V_max;
-  }
+  // Clamp the filter to middle range (25% to 75%)
+  // Not necessary when the filter is initialized at mid-range.
+
+  // const uint32_t lo = (128UL * 25/100) << 24;
+  // const uint32_t hi = (128UL * 75/100) << 24;
+
+  // if (l_filterDC_V[phase] < lo)
+  //   l_filterDC_V[phase] = lo;
+
+  // if (l_filterDC_V[phase] > hi)
+  //   l_filterDC_V[phase] = hi;
 }
 
 /**
@@ -1129,46 +1132,49 @@ ISR(ADC_vect)
   static uint8_t sample_index{ 0 };
   int16_t rawSample;
 
+  // Default ADC ADMUX, ADC left aligned
+  constexpr uint8_t admux{ bit(ADLAR) | bit(REFS0) };
+
   switch (sample_index)
   {
     case 0:
       rawSample = ADC;                  // store the ADC value (this one is for Voltage L1)
-      ADMUX = bit(REFS0) + sensorV[1];  // the conversion for I1 is already under way
+      ADMUX = admux | sensorV[1];       // the conversion for I1 is already under way
       ++sample_index;                   // increment the control flag
       //
       processVoltageRawSample(0, rawSample);
       break;
     case 1:
       rawSample = ADC;                  // store the ADC value (this one is for Current L1)
-      ADMUX = bit(REFS0) + sensorI[1];  // the conversion for V2 is already under way
+      ADMUX = admux | sensorI[1];       // the conversion for V2 is already under way
       ++sample_index;                   // increment the control flag
       //
       processCurrentRawSample(0, rawSample);
       break;
     case 2:
       rawSample = ADC;                  // store the ADC value (this one is for Voltage L2)
-      ADMUX = bit(REFS0) + sensorV[2];  // the conversion for I2 is already under way
+      ADMUX = admux | sensorV[2];       // the conversion for I2 is already under way
       ++sample_index;                   // increment the control flag
       //
       processVoltageRawSample(1, rawSample);
       break;
     case 3:
       rawSample = ADC;                  // store the ADC value (this one is for Current L2)
-      ADMUX = bit(REFS0) + sensorI[2];  // the conversion for V3 is already under way
+      ADMUX = admux | sensorI[2];       // the conversion for V3 is already under way
       ++sample_index;                   // increment the control flag
       //
       processCurrentRawSample(1, rawSample);
       break;
     case 4:
       rawSample = ADC;                  // store the ADC value (this one is for Voltage L3)
-      ADMUX = bit(REFS0) + sensorV[0];  // the conversion for I3 is already under way
+      ADMUX = admux | sensorV[0];       // the conversion for I3 is already under way
       ++sample_index;                   // increment the control flag
       //
       processVoltageRawSample(2, rawSample);
       break;
     case 5:
       rawSample = ADC;                  // store the ADC value (this one is for Current L3)
-      ADMUX = bit(REFS0) + sensorI[0];  // the conversion for V1 is already under way
+      ADMUX = admux | sensorI[0];       // the conversion for V1 is already under way
       sample_index = 0;                 // reset the control flag
       //
       processCurrentRawSample(2, rawSample);

Changes:

Changed the ADC conversion to use left alignment to simplify the math.
Increased the ADC accuracy by 0.1 LSB.
Increased the filter time constant from ~10 seconds to ~60 seconds.
Fixed the initial state of the low pass filter for the bias.
Exclude the CT filters from the compilation when the factors are zero.

Uh oh!

Suggestions 1 & 2 #121

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