arm-cortex-r82: Add MPU support

This commit introduces support for the Memory Protection Unit (MPU)
to the ARM Cortex-R82 port. The MPU enhances system security
by allowing the definition of memory regions with specific access
permissions. The following changes have been made:
- Added MPU configuration functions in `port.c` to set up memory
  regions and their attributes.
- Updated `portASM.S` to include assembly routines for MPU
  and context switching with MPU support.
- Created `mpu_wrappers_v2_asm.c` to provide assembly wrappers for
  MPU operations.
- Updated `portmacro.h` to include MPU-related macros and definitions.
- Modified `task.h` to include MPU-related task attributes.
- Updated `CMakeLists.txt` to include the new MPU source file.
- Enhanced the `README.md` with instructions on MPU configuration.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>

Author: AhmedIsmail02

.github/.cSpellWords.txt

@@ -70,6 +70,7 @@ CANTX
 capitalisation
 cbmc
 CBMC
+cbnz
 cbor
 CBOR
 CCIE
@@ -108,6 +109,8 @@ CLKS
 CLKSOURCE
 CLKSTA
 CLRB
+clrex
+CLREX
 CLRF
 clrm
 CLRPSW
@@ -379,6 +382,7 @@ IFSR
 imajeff
 INACK
 INDF
+initialisations
 inpw
 INTE
 INTFRCH
@@ -652,18 +656,24 @@ PPUDR
 PPUER
 PPUSR
 ppux
+Prbar
+PRBAR
 PRCR
 PREA
 PREB
 PRIA
 Prioritised
 PRIS
 PRIVDEFENA
+Prlar
+PRLAR
 PROCDLY
 PRODH
 PRODL
 PROGE
 Prokic
+Prselr
+PRSELR
 prtmacro
 psha
 psplim
@@ -706,6 +716,7 @@ REENT
 REGA
 RELD
 Renesas
+restoreallgpregisters
 reta
 reti
 RETP
@@ -773,6 +784,8 @@ SCBR
 SCDR
 SCER
 SCSR
+Sctlr
+SCTLR
 SDCC
 SECU
 SENDA
@@ -930,6 +943,7 @@ UNSUB
 UNSUBACK
 unsubscriptions
 unsuspended
+unupdated
 UPAC
 URAD
 URAT

.github/scripts/kernel_checker.py

@@ -119,6 +119,7 @@
     r'.*portable/.*/ARM_CM4_MPU*',
     r'.*portable/.*/ARM_CM4F_MPU*',
     r'.*portable/.*/ARM_CR82*',
+    r'.*include/task\.h$',
 ]
 
 KERNEL_HEADER = [

include/task.h

@@ -1,6 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -68,18 +69,21 @@
 #if defined( portARMV8M_MINOR_VERSION ) && ( portARMV8M_MINOR_VERSION >= 1 )
     #define tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER    ( 1U << 5U )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
+#define tskMPU_REGION_NON_SHAREABLE                   ( 1U << 6U )
+#define tskMPU_REGION_OUTER_SHAREABLE                 ( 1U << 7U )
+#define tskMPU_REGION_INNER_SHAREABLE                 ( 1U << 8U )
 
 /* MPU region permissions stored in MPU settings to
  * authorize access requests. */
-#define tskMPU_READ_PERMISSION        ( 1U << 0U )
-#define tskMPU_WRITE_PERMISSION       ( 1U << 1U )
+#define tskMPU_READ_PERMISSION                        ( 1U << 0U )
+#define tskMPU_WRITE_PERMISSION                       ( 1U << 1U )
 
 /* The direct to task notification feature used to have only a single notification
  * per task.  Now there is an array of notifications per task that is dimensioned by
  * configTASK_NOTIFICATION_ARRAY_ENTRIES.  For backward compatibility, any use of the
  * original direct to task notification defaults to using the first index in the
  * array. */
-#define tskDEFAULT_INDEX_TO_NOTIFY    ( 0 )
+#define tskDEFAULT_INDEX_TO_NOTIFY                    ( 0 )
 
 /**
  * task. h

portable/CMakeLists.txt

@@ -243,7 +243,8 @@ add_library(freertos_kernel_port OBJECT
     # ARMv8-R ports for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CR82>:
         GCC/ARM_CR82/port.c
-        GCC/ARM_CR82/portASM.S>
+        GCC/ARM_CR82/portASM.S
+        GCC/ARM_CR82/mpu_wrappers_v2_asm.c>
 
     # ARMv4T ARM7TDMI ports for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM7_AT91FR40008>:
@@ -822,6 +823,7 @@ if( FREERTOS_PORT MATCHES "GCC_ARM_CM(3|4)_MPU" OR
     FREERTOS_PORT MATCHES "GCC_ARM_CM(23|33|52|55|85)_NTZ_NONSECURE" OR
     FREERTOS_PORT MATCHES "GCC_ARM_CM(23|33|52|55|85)_NONSECURE" OR
     FREERTOS_PORT MATCHES "GCC_ARM_CM(33|52|55|85)_TFM" OR
+    FREERTOS_PORT MATCHES "GCC_ARM_CR82" OR
     FREERTOS_PORT MATCHES "IAR_ARM_CM(23|33|52|55|85)_NTZ_NONSECURE" OR
     FREERTOS_PORT MATCHES "IAR_ARM_CM(23|33|52|55|85)_NONSECURE" OR
     FREERTOS_PORT MATCHES "IAR_ARM_CM(33|52|55|85)_TFM"

portable/GCC/ARM_CR82/README.md

@@ -18,6 +18,12 @@ The port is supported and tested on the following toolchains:
 - The port does not perform cache maintenance for shared buffers.
 - If your hardware or model doesn't support full cache coherency, you must handle cache clean/invalidate operations, memory attributes, and any additional barriers in your BSP/application (especially around shared-memory regions).
 
+# MPU Support
+
+- This port supports the FreeRTOS MPU on both single-core and SMP (multi-core) configurations. Enable via `configENABLE_MPU = 1`; the port programs MPU regions per task on each active core.
+
+- Minimum MPU granularity and alignment: 64 bytes. Ensure any user‑defined region base and size are 64‑byte aligned.
+
 # SMP Multicore Bring-up
 
 For SMP systems using this port, the application only needs to start the scheduler on the primary core and issue an SVC from each secondary core once they are online. The kernel coordinates the rest and ensures all cores are properly managed.
@@ -39,4 +45,4 @@ Secondary core flow (to be done in each core’s reset handler):
 2. Wait for the primary core's signal that shared initialization is complete (i.e., `ucPrimaryCoreInitDoneFlag` set to 1).
 3. Update `VBAR_EL1` from the boot vector table to the FreeRTOS vector table.
 4. Initialize the GIC redistributor and enable SGIs so interrupts from the primary core are receivable; signal the primary that this secondary is online and ready by setting the its flag in the `ucSecondaryCoresReadyFlags` array.
-5. Issue an SVC with immediate value `106` to enter `FreeRTOS_SWI_Handler`, which will call `vPortRestoreContext()` based on the SVC number to start scheduling on this core.
+5. Issue an SVC with immediate value `106` (i.e., `portSVC_START_FIRST_TASK`) to enter `FreeRTOS_SWI_Handler`, which will call `vPortRestoreContext()` based on the SVC number to start scheduling on this core.