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Remove redundant code and preprocessor directives
1 parent a8ae21c commit d5b2130

1 file changed

Lines changed: 12 additions & 19 deletions

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  • portable/ThirdParty/GCC/RP2040

portable/ThirdParty/GCC/RP2040/port.c

Lines changed: 12 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -243,35 +243,28 @@ void vPortStartFirstTask( void )
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" ldr r0, [r0] \n"
244244
" msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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#endif /* configRESET_STACK_POINTER */
246-
#if ( configNUMBER_OF_CORES != 1 )
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" adr r1, ulAsmLocals \n" /* Get the location of the current TCB for the current core. */
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" ldmia r1!, {r2, r3} \n"
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" ldr r2, [r2] \n" /* r2 = Core number */
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" lsls r2, #2 \n"
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" ldr r3, [r3, r2] \n" /* r3 = pxCurrentTCBs[get_core_num()] */
252-
#else /* configNUMBER_OF_CORES != 1 */
253-
" ldr r3, =pxCurrentTCBs \n"
254-
" ldr r3, [r3] \n" /* r3 = pxCurrentTCBs[0] */
255-
#endif /* configNUMBER_OF_CORES != 1 */
256-
" ldr r0, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
257-
" adds r0, #32 \n" /* Discard everything up to r0. */
258-
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
259-
" movs r0, #2 \n" /* Switch to the psp stack. */
260-
" msr CONTROL, r0 \n"
261-
" isb \n"
262-
" pop {r0-r5} \n" /* Pop the registers that are saved automatically. */
263-
" mov lr, r5 \n" /* lr is now in r5. */
264-
" pop {r3} \n" /* Return address is now in r3. */
265-
" pop {r2} \n" /* Pop and discard XPSR. */
266-
" cpsie i \n" /* The first task has its context and interrupts can be enabled. */
267-
" bx r3 \n" /* Finally, jump to the user defined task code. */
268-
#if configNUMBER_OF_CORES != 1
251+
" ldr r0, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
252+
" adds r0, #32 \n" /* Discard everything up to r0. */
253+
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
254+
" movs r0, #2 \n" /* Switch to the psp stack. */
255+
" msr CONTROL, r0 \n"
256+
" isb \n"
257+
" pop {r0-r5} \n" /* Pop the registers that are saved automatically. */
258+
" mov lr, r5 \n" /* lr is now in r5. */
259+
" pop {r3} \n" /* Return address is now in r3. */
260+
" pop {r2} \n" /* Pop and discard XPSR. */
261+
" cpsie i \n" /* The first task has its context and interrupts can be enabled. */
262+
" bx r3 \n" /* Finally, jump to the user defined task code. */
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" \n"
270264
" .align 4 \n"
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"ulAsmLocals: \n"
272266
" .word 0xD0000000 \n" /* SIO */
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" .word pxCurrentTCBs \n"
274-
#endif /* portRUNNING_ON_BOTH_CORES */
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);
276269
#endif /* if ( configNUMBER_OF_CORES == 1 ) */
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}

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