cortex-r82-smp-example: Add minor improvements

This commit adds multiple improvements to the
example and adapt to the latest port code changes.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>

Author: AhmedIsmail02

CORTEX_R82_SMP_FVP_GCC_ARMCLANG/BSP/CMakeLists.txt

@@ -10,7 +10,7 @@ target_sources(bsp
     INTERFACE
         ${CMAKE_CURRENT_SOURCE_DIR}/Source/port_asm_vectors.S
         ${CMAKE_CURRENT_SOURCE_DIR}/Source/boot.S
-        ${CMAKE_CURRENT_SOURCE_DIR}/Source/xil-crt0.S
+        ${CMAKE_CURRENT_SOURCE_DIR}/Source/startup.S
         ${CMAKE_CURRENT_SOURCE_DIR}/Source/gic.c
 )
 

CORTEX_R82_SMP_FVP_GCC_ARMCLANG/BSP/Include/gic.h

@@ -2,29 +2,38 @@
  * SPDX-License-Identifier: MIT
  */
 
-#define GICD_BASE                    ( 0xAF000000UL )                        /* Base of GIC Distributor on BaseR FVP */
-#define GICR_BASE_PER_CORE( core )   ( 0xAF100000 + (0x20000 * ( core ) ) )  /* Base of GIC Redistributor per core on BaseR FVP */
-#define SGI_BASE                     ( 0x10000 )                             /* SGI Base */
-#define GICD_CTLR                    ( 0x000 )                               /* Distributor Control Register */
-#define GICR_WAKER                   ( 0x14  )                               /* ReDistributor Wake Register */
-#define GICR_PWRR                    ( 0x24  )                               /* ReDistributor Power Register */
-#define GICR_IGROUPR0                ( SGI_BASE + 0x80 )                     /* Interrupt Group Registers */
-#define GICR_ISENABLER0              ( SGI_BASE + 0x100 )                    /* Interrupt Set-Enable Registers */
-#define GICR_IPRIORITYR( n )         ( SGI_BASE + ( 0x400 + ( 4 * n ) ) )    /* Interrupt Priority Registers */
-#define GICR_IGRPMODR0               ( SGI_BASE + 0xD00 )                    /* Distributor Interrupt group modifier Register */
+#ifndef GIC_H
+#define GIC_H
 
-#define GICD_CTLR_ENABLEGRP1NS_BIT   ( 1U )                                  /* GICD_CTRL.EnableGrp1NS bit */
-#define GICD_CTLR_ENABLEGRP1S_BIT    ( 2U )                                  /* GICD_CTRL.EnableGrp1S bit */
-#define GICD_CTLR_ARES_BIT           ( 4U )                                  /* GICD_CTRL.ARE_S bit */
-#define GICD_CTLR_DS_BIT             ( 6U )                                  /* GICD_CTRL.DS bit */
+#include "FreeRTOSConfig.h"
 
-#define GICR_PWRR_RDPD_BIT           ( 0U )                                  /* GICR_PWRR.RDPD bit */
+#if ( configNUMBER_OF_CORES == 1 )
+    #define ucPortGetCoreID()        ( 0 )                                          /* Single core system, always core 0 */
+#endif
 
-#define GICR_WAKER_PS_BIT            ( 1U )                                  /* GICR_WAKER.PS bit */
-#define GICR_WAKER_CA_BIT            ( 2U )                                  /* GICR_WAKER.CA bit */
+#define GICD_BASE                    ( 0xAF000000UL )                               /* Base of GIC Distributor on BaseR FVP */
+#define GICR_BASE_PER_CORE( core )   ( 0xAF100000UL + ( 0x20000UL * ( core ) ) )    /* Base of GIC Redistributor per core on BaseR FVP */
+#define SGI_BASE                     ( 0x10000UL )                                  /* SGI Base */
+#define GICD_CTLR                    ( 0x000 )                                      /* Distributor Control Register */
+#define GICR_WAKER                   ( 0x14  )                                      /* ReDistributor Wake Register */
+#define GICR_PWRR                    ( 0x24  )                                      /* ReDistributor Power Register */
+#define GICR_IGROUPR0                ( SGI_BASE + 0x80 )                            /* Interrupt Group Registers */
+#define GICR_ISENABLER0              ( SGI_BASE + 0x100 )                           /* Interrupt Set-Enable Registers */
+#define GICR_IPRIORITYR( n )         ( SGI_BASE + ( 0x400 + ( 4 * n ) ) )           /* Interrupt Priority Registers */
+#define GICR_IGRPMODR0               ( SGI_BASE + 0xD00 )                           /* Distributor Interrupt group modifier Register */
 
-#define GIC_MAX_INTERRUPT_ID         ( 31UL )                                /* Maximum Interrupt ID for PPIs and SGIs */
-#define GIC_WAIT_TIMEOUT             ( 1000000U )                            /* Timeout for waiting on GIC operations */
+#define GICD_CTLR_ENABLEGRP1NS_BIT   ( 1U )                                         /* GICD_CTRL.EnableGrp1NS bit */
+#define GICD_CTLR_ENABLEGRP1S_BIT    ( 2U )                                         /* GICD_CTRL.EnableGrp1S bit */
+#define GICD_CTLR_ARES_BIT           ( 4U )                                         /* GICD_CTRL.ARE_S bit */
+#define GICD_CTLR_DS_BIT             ( 6U )                                         /* GICD_CTRL.DS bit */
+
+#define GICR_PWRR_RDPD_BIT           ( 0U )                                         /* GICR_PWRR.RDPD bit */
+
+#define GICR_WAKER_PS_BIT            ( 1U )                                         /* GICR_WAKER.PS bit */
+#define GICR_WAKER_CA_BIT            ( 2U )                                         /* GICR_WAKER.CA bit */
+
+#define GIC_MAX_INTERRUPT_ID         ( 31UL )                                       /* Maximum Interrupt ID for PPIs and SGIs */
+#define GIC_WAIT_TIMEOUT             ( 1000000U )                                   /* Timeout for waiting on GIC operations */
 
 /**
  * Assigns the specified interrupt to Group 1 and enables it
@@ -66,3 +75,5 @@ void vGIC_SetPriority( uint32_t ulInterruptID, uint32_t ulPriority );
  * sets SGI0 to be a Group 1 interrupt, and enables delivery of Group-1 IRQs to EL1.
  */
 void vGIC_SetupSgi0( void );
+
+#endif /* GIC_H */

CORTEX_R82_SMP_FVP_GCC_ARMCLANG/BSP/Source/boot.S

@@ -48,6 +48,10 @@
     #error "Unsupported configNUMBER_OF_CORES value — must be a power‑of‑two up to 4"
 #endif
 
+.set SCTLR_EL1_NTWE,  18     /* SCTLR_EL1.nTWE bit position */
+.set SCTLR_EL1_NTWI,  16     /* SCTLR_EL1.nTWI bit position */
+.set SCTLR_EL1_CACHE, 2      /* SCTLR_EL1.C bit position */
+
 .section .boot,"ax"
 
 _prestart:
@@ -87,10 +91,11 @@ start:
 	mov      x30, #0
 
 	mrs	    x0, currentEL
+	/* Check we’ve come from EL1 (currentEL==0x4), otherwise fault */
 	cmp	    x0, #0x4
 	beq	    InitEL1
 
-	b 	    error			/* Check we’ve come from EL1 (currentEL==0x4), otherwise fault */
+	b 	    error
 InitEL1:
 	/* Set vector table base address */
 	ldr	    x1, =vector_base
@@ -103,8 +108,7 @@ InitEL1:
 	isb
 
 	/* Clear FP status flags (FPSR) to avoid spurious exceptions on first use */
-	mov  x0, 0x0
-	msr  FPSR, x0
+	msr  FPSR, xzr
 
 	/* Define stack pointer for current exception level */
 #if configNUMBER_OF_CORES > 1
@@ -120,8 +124,8 @@ InitEL1:
     /* x4 = this CPU’s index (Aff0 field of MPIDR_EL1) */
     mrs     x4,  MPIDR_EL1
     and     x4,  x4,  #0xFF         /* core_id ∈ {0 … N_CPUS-1} */
-	cmp     x4, #configNUMBER_OF_CORES
-	b.hs    error
+    cmp     x4, #configNUMBER_OF_CORES
+    b.hs    error
     /* x0 = slice_size * core_id  →  how far to step back from the top  */
     mul     x0,  x1,  x4
     /* sp = top_of_pool – offset   (so core 0 gets the very top) */
@@ -153,9 +157,9 @@ InitEL1:
 	 * - Allow EL0 to execute WFE/WFI (Set nTWE/nTWI so they don't trap)
 	 */
 	mrs     x1, SCTLR_EL1
-	orr     x1, x1, #(1 << 18)    /* nTWE = 1 → WFE at EL0 does not trap */
-	orr     x1, x1, #(1 << 16)    /* nTWI = 1 → WFI at EL0 does not trap */
-	orr     x1, x1, #(1 << 2)     /* C = 1   → enable data cache */
+	orr     x1, x1, #(1 << SCTLR_EL1_NTWE)    /* nTWE = 1 → WFE at EL0 does not trap */
+	orr     x1, x1, #(1 << SCTLR_EL1_NTWI)    /* nTWI = 1 → WFI at EL0 does not trap */
+	orr     x1, x1, #(1 << SCTLR_EL1_CACHE)   /* C = 1   → enable data cache */
 	msr     SCTLR_EL1, x1
 	isb
 

CORTEX_R82_SMP_FVP_GCC_ARMCLANG/BSP/Source/gic.c

@@ -2,7 +2,6 @@
  * SPDX-License-Identifier: MIT
  */
 
-#include <stdint.h>
 #include <stdio.h>
 #include "FreeRTOS.h"
 #include "FreeRTOSConfig.h"
@@ -22,8 +21,12 @@ void vGIC_EnableCPUInterface( void )
 
 void vGIC_PowerUpRedistributor( void )
 {
-    volatile uint32_t *pulPwrr = ( uint32_t * )( GICR_BASE_PER_CORE( xPortGetCoreID() ) + GICR_PWRR );
-    volatile uint32_t *pulWaker = ( uint32_t * )( GICR_BASE_PER_CORE( xPortGetCoreID() ) + GICR_WAKER );
+    volatile uint32_t *pulPwrr = ( volatile uint32_t * )( ( portPOINTER_SIZE_TYPE ) GICR_BASE_PER_CORE( ucPortGetCoreID() ) +
+                                                          ( portPOINTER_SIZE_TYPE ) GICR_PWRR );
+
+    volatile uint32_t *pulWaker = ( volatile uint32_t * )( ( portPOINTER_SIZE_TYPE ) GICR_BASE_PER_CORE( ucPortGetCoreID() ) +
+                                                           ( portPOINTER_SIZE_TYPE ) GICR_WAKER );
+
     uint32_t ulTimeout = GIC_WAIT_TIMEOUT;
 
     /* Clear RDPD (Redistributor Power-Down) to 0 → power on the redistributor */
@@ -59,10 +62,10 @@ void vGIC_InitDist( void )
     /* Enable Group-1 Non-Secure (NS) and Secure (S) interrupts, and turn on Affinity-routing (ARE_S)
      *plus Disable-Security (DS) for full GICv3 operation
      */
-    *( volatile uint32_t * )( GICD_BASE + GICD_CTLR )  = ( 1 << GICD_CTLR_ENABLEGRP1NS_BIT ) |
-                                                         ( 1 << GICD_CTLR_ENABLEGRP1S_BIT )  |
-                                                         ( 1 << GICD_CTLR_ARES_BIT )         |
-                                                         ( 1 << GICD_CTLR_DS_BIT );
+    *( volatile uint32_t * )( ( portPOINTER_SIZE_TYPE ) GICD_BASE + ( portPOINTER_SIZE_TYPE ) GICD_CTLR )  = ( 1 << GICD_CTLR_ENABLEGRP1NS_BIT ) |
+                                                                                                             ( 1 << GICD_CTLR_ENABLEGRP1S_BIT )  |
+                                                                                                             ( 1 << GICD_CTLR_ARES_BIT )         |
+                                                                                                             ( 1 << GICD_CTLR_DS_BIT );
 
     /* Ensure distributor configuration is visible before continuing */
     __asm volatile ( "dsb sy" ::: "memory" );
@@ -78,7 +81,8 @@ void vGIC_SetPriority( uint32_t ulInterruptID, uint32_t ulPriority )
         uint32_t ulShift  = ( ulInterruptID % 4U ) * 8U; /* Byte lane offset */
         uint32_t ulMask   = 0xFFUL << ulShift;           /* Field mask       */
 
-        volatile uint32_t * pulPriorityReg = ( volatile uint32_t * ) ( ( uintptr_t ) GICR_BASE_PER_CORE( xPortGetCoreID() ) + GICR_IPRIORITYR( ulIndex ) );
+        volatile uint32_t * pulPriorityReg = ( volatile uint32_t * ) ( ( portPOINTER_SIZE_TYPE ) GICR_BASE_PER_CORE( ucPortGetCoreID() ) +
+                                                                       ( portPOINTER_SIZE_TYPE ) GICR_IPRIORITYR( ulIndex ) );
         uint32_t ulRegValue = *pulPriorityReg;
         ulRegValue &= ~( ulMask );
         ulRegValue |= ( ( uint32_t ) ulPriority << ulShift );
@@ -99,10 +103,10 @@ void vGIC_EnableIRQ( uint32_t ulInterruptID )
         uint32_t ulBitMask   = 1U << ulInterruptID;
 
         /* 1. Assign the interrupt to group 1 */
-        *( volatile uint32_t * )( GICR_BASE_PER_CORE( xPortGetCoreID() ) + GICR_IGROUPR0 )  |= ( 1U << ulInterruptID );
+        *( volatile uint32_t * )( ( portPOINTER_SIZE_TYPE ) GICR_BASE_PER_CORE( ucPortGetCoreID() ) + ( portPOINTER_SIZE_TYPE ) GICR_IGROUPR0 )  |= ( 1U << ulInterruptID );
 
         /* 2. Enable the interrupt in GIC */
-        *( volatile uint32_t* )( GICR_BASE_PER_CORE( xPortGetCoreID() ) + GICR_ISENABLER0 ) |= ulBitMask;
+        *( volatile uint32_t* )( ( portPOINTER_SIZE_TYPE ) GICR_BASE_PER_CORE( ucPortGetCoreID() ) + ( portPOINTER_SIZE_TYPE ) GICR_ISENABLER0 ) |= ulBitMask;
 
         /* Ensure interrupt enable is visible */
         __asm volatile ( "dsb sy" ::: "memory" );

…P_FVP_GCC_ARMCLANG/BSP/Source/xil-crt0.S …MP_FVP_GCC_ARMCLANG/BSP/Source/startup.SCORTEX_R82_SMP_FVP_GCC_ARMCLANG/BSP/Source/xil-crt0.S renamed to CORTEX_R82_SMP_FVP_GCC_ARMCLANG/BSP/Source/startup.S CORTEX_R82_SMP_FVP_GCC_ARMCLANG/BSP/Source/xil-crt0.S renamed to CORTEX_R82_SMP_FVP_GCC_ARMCLANG/BSP/Source/startup.S

@@ -13,7 +13,8 @@
 #endif
 
 #include "FreeRTOSConfig.h"
-	.file	"xil-crt0.S"
+#include "portmacro.h"
+	.file	"startup.S"
 	.align	2
 
 .extern _vector_table
@@ -98,6 +99,7 @@ c_init_end:
 #endif
 	b	    jump_to_main
 
+#if configNUMBER_OF_CORES > 1
 secondary_cores_hold:
     ldr     x0, =ucPrimaryCoreInitDoneFlag
     ldr     w1, [x0]               			/* Has the primary core set the flag? */
@@ -115,11 +117,12 @@ make_secondary_cores_ready:
 	ldr  x0, =ucSecondaryCoresReadyFlags
 	mrs  x1, MPIDR_EL1
 	and  x1, x1, #0xFF
-	sub  x1, x1, #1             /* Core 1 is index 0 in the array */
+	sub  x1, x1, #1                 /* Core 1 is index 0 in the array */
 	add	 x0, x0, x1
 	mov  w1, #1
-	strb w1, [x0]               /* Mark this core as ready */
-	SVC 106                     /* Start the first task on the secondary core */
+	strb w1, [x0]                   /* Mark this core as ready */
+	SVC  # portSVC_START_FIRST_TASK /* Start the first task on the secondary core */
+#endif
 
 jump_to_main:
 	ldr     X1, = freertos_vector_base

CORTEX_R82_SMP_FVP_GCC_ARMCLANG/LICENSE.md

@@ -0,0 +1,21 @@
+MIT License
+
+Copyright 2025-2026 Arm Limited and/or its affiliates <open-source-office@arm.com>
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

CORTEX_R82_SMP_FVP_GCC_ARMCLANG/README.md

@@ -59,7 +59,7 @@ This example relies on the `FVP_BaseR_AEMv8R` implementing fully coherent caches
 | **Shared flag** | `ulSharedFlag` (64-bit) is cache-coherent across cores. |
 | **Tasks** | `prvTaskCore0` (core 0) prints **Ping**, sets flag to 1; `prvTaskCore1` (core 1) prints **Pong**, sets flag to 0. Each task delays for 1 s (`vTaskDelay( pdMS_TO_TICKS(1000) )`). |
 | **Core affinity** | After creation, tasks are pinned via `vTaskCoreAffinitySet()` to ensure deterministic execution. |
-| **Scheduler bring-up** | Only primary Core (i.e., Core 0) jumps to main, creates the user tasks, and calls `vTaskStartScheduler()`. Each secondary core starts and does all the its core specific initialisation and spin in `wfe` until `ucPrimaryCoreInitDoneFlag` is set to `1`, initialize the GIC redistributor and enable SGIs so interrupts from the primary core are receivable, signal the primary core that this secondary core is online and ready by setting the its flag in the `ucSecondaryCoresReadyFlags` array, finally issues an SVC with immediate value `106` to enter `FreeRTOS_SWI_Handler`, which will call `vPortRestoreContext()` based on the SVC number to start scheduling on the secondary core. |
+| **Scheduler bring-up** | Only primary Core (i.e., Core 0) jumps to main, creates the user tasks, and calls `vTaskStartScheduler()`. Each secondary core starts and does all the its core specific initialisation and spin in `wfe` until `ucPrimaryCoreInitDoneFlag` is set to `1`, initialize the GIC redistributor and enable SGIs so interrupts from the primary core are receivable, signal the primary core that this secondary core is online and ready by setting the its flag in the `ucSecondaryCoresReadyFlags` array, finally issues an SVC with immediate value `106` (i.e., `portSVC_START_FIRST_TASK`) to enter `FreeRTOS_SWI_Handler`, which will call `vPortRestoreContext()` based on the SVC number to start scheduling on the secondary core. |
 | **Tick timer** | `vConfigureTickInterrupt()` programs `CNTP_EL0` for the FreeRTOS tick and routes `IRQ 30` through the GIC to all cores. |
 | **Cache maintenance** | Each write to `ulSharedFlag` is followed by a `DSB SY` to guarantee visibility before the other core wakes. |
 
@@ -134,4 +134,4 @@ Rebuild the example and launch the model as usual.
 
 ## License
 
-This example is released under the **MIT License**.
+This example is released under the **MIT License**. See the [LICENSE](LICENSE.md) file.

CORTEX_R82_SMP_FVP_GCC_ARMCLANG/armclang_toolchain.cmake

@@ -15,8 +15,8 @@ set(CMAKE_C_STANDARD         11)
 set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
 
 # Common flags for compilation
-set(CMAKE_C_FLAGS "--target=aarch64-arm-none-eabi -mcpu=cortex-r82 -mlittle-endian -Werror -g -gdwarf-3 -mstrict-align" )
-set(CMAKE_ASM_FLAGS "--target=aarch64-arm-none-eabi -mcpu=cortex-r82 -Werror -g -gdwarf-3 -mstrict-align" )
+set(CMAKE_C_FLAGS "--target=aarch64-arm-none-eabi -mcpu=cortex-r82 -mlittle-endian -Werror -mstrict-align" )
+set(CMAKE_ASM_FLAGS "--target=aarch64-arm-none-eabi -mcpu=cortex-r82 -Werror -mstrict-align" )
 
 set(CMAKE_EXE_LINKER_FLAGS_INIT    "--entry=_boot" )
 set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS_INIT}")

CORTEX_R82_SMP_FVP_GCC_ARMCLANG/gnu_toolchain.cmake

@@ -11,8 +11,8 @@ set(CMAKE_ASM_COMPILER "aarch64-none-elf-gcc")
 
 set(CMAKE_C_STANDARD 11)
 
-set(CMAKE_C_FLAGS "-mcpu=cortex-r82 -mabi=lp64 -mlittle-endian -Wall -Wextra -g -gdwarf-3 -mstrict-align")
-set(CMAKE_ASM_FLAGS "-mcpu=cortex-r82 -mabi=lp64 -Wall -g -gdwarf-3")
+set(CMAKE_C_FLAGS "-mcpu=cortex-r82 -mabi=lp64 -mlittle-endian -Wall -Wextra -Werror -mstrict-align")
+set(CMAKE_ASM_FLAGS "-mcpu=cortex-r82 -mabi=lp64 -Wall -Werror -mstrict-align")
 
 set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
 

CORTEX_R82_SMP_FVP_GCC_ARMCLANG/main.c

@@ -63,7 +63,7 @@ static void prvTaskCore0( void * arg )
         {
             if( ulSharedFlag == 0U )
             {
-                printf( "Ping from Core %lu\r\n", xPortGetCoreID() );
+                printf( "Ping from Core %d\r\n", ucPortGetCoreID() );
                 ulSharedFlag = 1U;
                 __asm volatile( "dsb sy");
             }
@@ -83,7 +83,7 @@ static void prvTaskCore1( void * arg )
         {
             if( ulSharedFlag == 1U )
             {
-                printf( "Pong from Core %lu\r\n", xPortGetCoreID() );
+                printf( "Pong from Core %d\r\n", ucPortGetCoreID() );
                 ulSharedFlag = 0U;
                 __asm volatile( "dsb sy");
             }
@@ -116,8 +116,10 @@ int main()
         return EXIT_FAILURE;
     }
 
-    vTaskCoreAffinitySet( prvTaskCore0Handle, 1UL << 0 );  /* Pin to Core 0 */
-    vTaskCoreAffinitySet( prvTaskCore1Handle, 1UL << 1 );  /* Pin to Core 1 */
+    #if ( configNUMBER_OF_CORES > 1 )
+        vTaskCoreAffinitySet( prvTaskCore0Handle, 1UL << 0 );  /* Pin to Core 0 */
+        vTaskCoreAffinitySet( prvTaskCore1Handle, 1UL << 1 );  /* Pin to Core 1 */
+    #endif
 
     xSharedFlagMutex = xSemaphoreCreateMutex();
 
@@ -266,10 +268,12 @@ void vApplicationIRQHandler( uint32_t ulICCIAR )
     {
         FreeRTOS_Tick_Handler();
     }
-    else if( ulInterruptID == SGI0_IRQ )
-    {
-        FreeRTOS_SGI_Handler();
-    }
+    #if ( configNUMBER_OF_CORES > 1 )
+        else if( ulInterruptID == SGI0_IRQ )
+        {
+            FreeRTOS_SGI_Handler();
+        }
+    #endif
     else
     {
         /* Handle other interrupts as needed. */