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Zhen Leiarndb
Zhen Lei
authored and
arndb
committed
arm64: dts: qcom: clear the warnings caused by empty dma-ranges
The scripts/dtc/checks.c requires that the node have empty "dma-ranges" property must have the same "#address-cells" and "#size-cells" values as the parent node. Otherwise, the following warnings is reported: arch/arm64/boot/dts/qcom/ipq6018.dtsi:185.3-14: Warning \ (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but \ its #address-cells (1) differs from / (2) arch/arm64/boot/dts/qcom/ipq6018.dtsi:185.3-14: Warning \ (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but \ its #size-cells (1) differs from / (2) Arnd Bergmann figured out why it's necessary: Also note that the #address-cells=<1> means that any device under this bus is assumed to only support 32-bit addressing, and DMA will have to go through a slow swiotlb in the absence of an IOMMU. Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20201016090833.1892-3-thunder.leizhen@huawei.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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‎arch/arm64/boot/dts/qcom/ipq6018.dtsi‎

Lines changed: 36 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -179,22 +179,22 @@
179179
};
180180

181181
soc: soc {
182-
#address-cells = <1>;
183-
#size-cells = <1>;
184-
ranges = <0 0 0 0xffffffff>;
182+
#address-cells = <2>;
183+
#size-cells = <2>;
184+
ranges = <0 0 0 0 0x0 0xffffffff>;
185185
dma-ranges;
186186
compatible = "simple-bus";
187187

188188
prng: qrng@e1000 {
189189
compatible = "qcom,prng-ee";
190-
reg = <0xe3000 0x1000>;
190+
reg = <0x0 0xe3000 0x0 0x1000>;
191191
clocks = <&gcc GCC_PRNG_AHB_CLK>;
192192
clock-names = "core";
193193
};
194194

195195
cryptobam: dma@704000 {
196196
compatible = "qcom,bam-v1.7.0";
197-
reg = <0x00704000 0x20000>;
197+
reg = <0x0 0x00704000 0x0 0x20000>;
198198
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
199199
clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
200200
clock-names = "bam_clk";
@@ -206,7 +206,7 @@
206206

207207
crypto: crypto@73a000 {
208208
compatible = "qcom,crypto-v5.1";
209-
reg = <0x0073a000 0x6000>;
209+
reg = <0x0 0x0073a000 0x0 0x6000>;
210210
clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
211211
<&gcc GCC_CRYPTO_AXI_CLK>,
212212
<&gcc GCC_CRYPTO_CLK>;
@@ -217,7 +217,7 @@
217217

218218
tlmm: pinctrl@1000000 {
219219
compatible = "qcom,ipq6018-pinctrl";
220-
reg = <0x01000000 0x300000>;
220+
reg = <0x0 0x01000000 0x0 0x300000>;
221221
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
222222
gpio-controller;
223223
#gpio-cells = <2>;
@@ -235,7 +235,7 @@
235235

236236
gcc: gcc@1800000 {
237237
compatible = "qcom,gcc-ipq6018";
238-
reg = <0x01800000 0x80000>;
238+
reg = <0x0 0x01800000 0x0 0x80000>;
239239
clocks = <&xo>, <&sleep_clk>;
240240
clock-names = "xo", "sleep_clk";
241241
#clock-cells = <1>;
@@ -244,17 +244,17 @@
244244

245245
tcsr_mutex_regs: syscon@1905000 {
246246
compatible = "syscon";
247-
reg = <0x01905000 0x8000>;
247+
reg = <0x0 0x01905000 0x0 0x8000>;
248248
};
249249

250250
tcsr_q6: syscon@1945000 {
251251
compatible = "syscon";
252-
reg = <0x01945000 0xe000>;
252+
reg = <0x0 0x01945000 0x0 0xe000>;
253253
};
254254

255255
blsp_dma: dma@7884000 {
256256
compatible = "qcom,bam-v1.7.0";
257-
reg = <0x07884000 0x2b000>;
257+
reg = <0x0 0x07884000 0x0 0x2b000>;
258258
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
259259
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
260260
clock-names = "bam_clk";
@@ -264,7 +264,7 @@
264264

265265
blsp1_uart3: serial@78b1000 {
266266
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
267-
reg = <0x078b1000 0x200>;
267+
reg = <0x0 0x078b1000 0x0 0x200>;
268268
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
269269
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
270270
<&gcc GCC_BLSP1_AHB_CLK>;
@@ -276,7 +276,7 @@
276276
compatible = "qcom,spi-qup-v2.2.1";
277277
#address-cells = <1>;
278278
#size-cells = <0>;
279-
reg = <0x078b5000 0x600>;
279+
reg = <0x0 0x078b5000 0x0 0x600>;
280280
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
281281
spi-max-frequency = <50000000>;
282282
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
@@ -291,7 +291,7 @@
291291
compatible = "qcom,spi-qup-v2.2.1";
292292
#address-cells = <1>;
293293
#size-cells = <0>;
294-
reg = <0x078b6000 0x600>;
294+
reg = <0x0 0x078b6000 0x0 0x600>;
295295
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
296296
spi-max-frequency = <50000000>;
297297
clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
@@ -306,7 +306,7 @@
306306
compatible = "qcom,i2c-qup-v2.2.1";
307307
#address-cells = <1>;
308308
#size-cells = <0>;
309-
reg = <0x078b6000 0x600>;
309+
reg = <0x0 0x078b6000 0x0 0x600>;
310310
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
311311
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
312312
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
@@ -321,7 +321,7 @@
321321
compatible = "qcom,i2c-qup-v2.2.1";
322322
#address-cells = <1>;
323323
#size-cells = <0>;
324-
reg = <0x078b7000 0x600>;
324+
reg = <0x0 0x078b7000 0x0 0x600>;
325325
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
326326
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
327327
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
@@ -336,24 +336,24 @@
336336
compatible = "qcom,msm-qgic2";
337337
interrupt-controller;
338338
#interrupt-cells = <0x3>;
339-
reg = <0x0b000000 0x1000>, /*GICD*/
340-
<0x0b002000 0x1000>, /*GICC*/
341-
<0x0b001000 0x1000>, /*GICH*/
342-
<0x0b004000 0x1000>; /*GICV*/
339+
reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/
340+
<0x0 0x0b002000 0x0 0x1000>, /*GICC*/
341+
<0x0 0x0b001000 0x0 0x1000>, /*GICH*/
342+
<0x0 0x0b004000 0x0 0x1000>; /*GICV*/
343343
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
344344
};
345345

346346
watchdog@b017000 {
347347
compatible = "qcom,kpss-wdt";
348348
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
349-
reg = <0x0b017000 0x40>;
349+
reg = <0x0 0x0b017000 0x0 0x40>;
350350
clocks = <&sleep_clk>;
351351
timeout-sec = <10>;
352352
};
353353

354354
apcs_glb: mailbox@b111000 {
355355
compatible = "qcom,ipq6018-apcs-apps-global";
356-
reg = <0x0b111000 0x1000>;
356+
reg = <0x0 0x0b111000 0x0 0x1000>;
357357
#clock-cells = <1>;
358358
clocks = <&a53pll>, <&xo>;
359359
clock-names = "pll", "xo";
@@ -362,7 +362,7 @@
362362

363363
a53pll: clock@b116000 {
364364
compatible = "qcom,ipq6018-a53pll";
365-
reg = <0x0b116000 0x40>;
365+
reg = <0x0 0x0b116000 0x0 0x40>;
366366
#clock-cells = <0>;
367367
clocks = <&xo>;
368368
clock-names = "xo";
@@ -377,68 +377,68 @@
377377
};
378378

379379
timer@b120000 {
380-
#address-cells = <1>;
381-
#size-cells = <1>;
380+
#address-cells = <2>;
381+
#size-cells = <2>;
382382
ranges;
383383
compatible = "arm,armv7-timer-mem";
384-
reg = <0x0b120000 0x1000>;
384+
reg = <0x0 0x0b120000 0x0 0x1000>;
385385
clock-frequency = <19200000>;
386386

387387
frame@b120000 {
388388
frame-number = <0>;
389389
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
390390
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
391-
reg = <0x0b121000 0x1000>,
392-
<0x0b122000 0x1000>;
391+
reg = <0x0 0x0b121000 0x0 0x1000>,
392+
<0x0 0x0b122000 0x0 0x1000>;
393393
};
394394

395395
frame@b123000 {
396396
frame-number = <1>;
397397
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
398-
reg = <0xb123000 0x1000>;
398+
reg = <0x0 0xb123000 0x0 0x1000>;
399399
status = "disabled";
400400
};
401401

402402
frame@b124000 {
403403
frame-number = <2>;
404404
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
405-
reg = <0x0b124000 0x1000>;
405+
reg = <0x0 0x0b124000 0x0 0x1000>;
406406
status = "disabled";
407407
};
408408

409409
frame@b125000 {
410410
frame-number = <3>;
411411
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
412-
reg = <0x0b125000 0x1000>;
412+
reg = <0x0 0x0b125000 0x0 0x1000>;
413413
status = "disabled";
414414
};
415415

416416
frame@b126000 {
417417
frame-number = <4>;
418418
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
419-
reg = <0x0b126000 0x1000>;
419+
reg = <0x0 0x0b126000 0x0 0x1000>;
420420
status = "disabled";
421421
};
422422

423423
frame@b127000 {
424424
frame-number = <5>;
425425
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
426-
reg = <0x0b127000 0x1000>;
426+
reg = <0x0 0x0b127000 0x0 0x1000>;
427427
status = "disabled";
428428
};
429429

430430
frame@b128000 {
431431
frame-number = <6>;
432432
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
433-
reg = <0x0b128000 0x1000>;
433+
reg = <0x0 0x0b128000 0x0 0x1000>;
434434
status = "disabled";
435435
};
436436
};
437437

438438
q6v5_wcss: remoteproc@cd00000 {
439439
compatible = "qcom,ipq8074-wcss-pil";
440-
reg = <0x0cd00000 0x4040>,
441-
<0x004ab000 0x20>;
440+
reg = <0x0 0x0cd00000 0x0 0x4040>,
441+
<0x0 0x004ab000 0x0 0x20>;
442442
reg-names = "qdsp6",
443443
"rmb";
444444
interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,

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