Phase 5: strip-based cascade DWT with cross-resolution pipelining

5a: StripBuffer - circular stripe buffer for cache-friendly DWT
5b: Cascade V-DWT kernels (v_cascade_p0_53, v_cascade_p1_53,
    v_cascade_53, v_cascade_strip_53) with bounded output ranges
5c: Strip-aware T1 scheduling - T1 blocks signal per-strip gates
    based on geometric overlap with strip partitions
5d: Cross-resolution pipelining - strips at resolution R signal
    dependent strips at resolution R+1 directly (no fan-out relay),
    enabling maximum concurrency across the resolution cascade

Author: Grok Compression