cache implementation

Write-through (No queue)
LRU

Block Diagram

links:

https://github.com/masoud-ata/PH-RISC-V https://github.com/masoud-ata/riscv_sv

https://github.com/vsaljooghi/RTL-Model-L1Caches (https://www.dropbox.com/scl/fi/43cswvmc57nt80thi8g9s/carpe-l1cache.tar.xz?rlkey=0fgce3k3k89cnmq68vvr4jb51&st=h28129du&dl=0)

https://www.youtube.com/watch?v=eVRdfl4zxfI https://www.youtube.com/user/NCSUDigitalASIC/playlists