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1 parent 77d1aa3 commit 60b988d

10 files changed

Lines changed: 183 additions & 177 deletions

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‎src/Emulator/Core/CPU/InstructionsImpl/ADC.cpp‎

Lines changed: 26 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
1919
static_assert(std::is_same_v<T1, T2>); // Locked by current CPU specification
2020

2121
cpu.ovf = AdditionWillOverflow(op1.deref<T1>(), op2.deref<T2>());
22-
op1.deref<T1>() = HyperALU::__hcpu_add(op1.deref<T1>(), HyperCPU::bit_cast_from<T2>(op2.ptr<T2>()));
22+
op1.deref<T1>() = HyperALU::__hcpu_add<T1>(op1.deref<T1>(), HyperCPU::bit_cast_from<T1>(op2.ptr<T2>()));
2323

2424
if (cpu.crf)
2525
++op1.deref<T1>();
@@ -34,7 +34,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
3434
T1 val = cpu.mem_controller->Read<T1>(ptr);
3535
cpu.ovf = AdditionWillOverflow(op1.deref<T1>(), val);
3636

37-
op1.deref<T1>() = HyperALU::__hcpu_add(op1.deref<T1>(), val);
37+
op1.deref<T1>() = HyperALU::__hcpu_add<T1>(op1.deref<T1>(), val);
3838

3939
if (cpu.crf)
4040
++op1.deref<T1>();
@@ -49,7 +49,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
4949
T1 val = cpu.mem_controller->Read<T1>(ptr);
5050
cpu.ovf = AdditionWillOverflow(op1.deref<T1>(), val);
5151

52-
op1.deref<T1>() = HyperALU::__hcpu_add(op1.deref<T1>(), val);
52+
op1.deref<T1>() = HyperALU::__hcpu_add<T1>(op1.deref<T1>(), val);
5353

5454
if (cpu.crf)
5555
++op1.deref<T1>();
@@ -62,26 +62,28 @@ class HyperCPU::CPU::CPU_InstrImpl {
6262

6363
T1 val = HyperCPU::bit_cast<T1>(op2);
6464
cpu.ovf = AdditionWillOverflow(op1.deref<T1>(), val);
65-
op1.deref<T1>() = HyperALU::__hcpu_add(op1.deref<T1>(), val);
65+
op1.deref<T1>() = HyperALU::__hcpu_add<T1>(op1.deref<T1>(), val);
6666

6767
if (cpu.crf)
6868
++op1.deref<T1>();
6969
}
7070
};
7171

72+
/*
7273
template<typename T1, typename TImpl>
7374
[[gnu::always_inline]]
7475
void ResolveOP2Mode(HyperCPU::Mode md2, HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, HyperCPU::CPU& cpu) {
7576
TImpl impl;
7677
7778
switch (md2) {
78-
case HyperCPU::Mode::b8: impl.template invoke<T1, std::uint8_t>(op1, op2, cpu); break;
79-
case HyperCPU::Mode::b16: impl.template invoke<T1, std::uint16_t>(op1, op2, cpu); break;
80-
case HyperCPU::Mode::b32: impl.template invoke<T1, std::uint32_t>(op1, op2, cpu); break;
81-
case HyperCPU::Mode::b64: impl.template invoke<T1, std::uint64_t>(op1, op2, cpu); break;
79+
case HyperCPU::Mode::b8: CPU_InstrImpl::template invoke<T1, std::uint8_t>(op1, op2, cpu); break;
80+
case HyperCPU::Mode::b16: CPU_InstrImpl::template invoke<T1, std::uint16_t>(op1, op2, cpu); break;
81+
case HyperCPU::Mode::b32: CPU_InstrImpl::template invoke<T1, std::uint32_t>(op1, op2, cpu); break;
82+
case HyperCPU::Mode::b64: CPU_InstrImpl::template invoke<T1, std::uint64_t>(op1, op2, cpu); break;
8283
default: std::abort();
8384
}
8485
}
86+
*/
8587

8688
void HyperCPU::CPU::ExecADC(const IInstruction& instr, OperandContainer op1, OperandContainer op2) {
8789
CPU_InstrImpl impl;
@@ -96,16 +98,16 @@ void HyperCPU::CPU::ExecADC(const IInstruction& instr, OperandContainer op1, Ope
9698
/* ADC R_R does not support different register sizes - we can call implementation directly */
9799
switch (instr.m_opcode_mode.md1) {
98100
case Mode::b8:
99-
impl.__hcpu_adc_rr_impl<std::uint8_t, std::uint8_t>(op1, op2, *this);
101+
CPU_InstrImpl::__hcpu_adc_rr_impl<std::uint8_t, std::uint8_t>(op1, op2, *this);
100102
break;
101103
case Mode::b16:
102-
impl.__hcpu_adc_rr_impl<std::uint16_t, std::uint16_t>(op1, op2, *this);
104+
CPU_InstrImpl::__hcpu_adc_rr_impl<std::uint16_t, std::uint16_t>(op1, op2, *this);
103105
break;
104106
case Mode::b32:
105-
impl.__hcpu_adc_rr_impl<std::uint32_t, std::uint32_t>(op1, op2, *this);
107+
CPU_InstrImpl::__hcpu_adc_rr_impl<std::uint32_t, std::uint32_t>(op1, op2, *this);
106108
break;
107109
case Mode::b64:
108-
impl.__hcpu_adc_rr_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
110+
CPU_InstrImpl::__hcpu_adc_rr_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
109111
break;
110112
}
111113
break;
@@ -120,16 +122,16 @@ void HyperCPU::CPU::ExecADC(const IInstruction& instr, OperandContainer op1, Ope
120122
/* ADC R_RM does not support different register sizes - we can call implementation directly */
121123
switch (instr.m_opcode_mode.md1) {
122124
case Mode::b8:
123-
impl.__hcpu_adc_rrm_impl<std::uint8_t, std::uint64_t>(op1, op2, *this);
125+
CPU_InstrImpl::__hcpu_adc_rrm_impl<std::uint8_t, std::uint64_t>(op1, op2, *this);
124126
break;
125127
case Mode::b16:
126-
impl.__hcpu_adc_rrm_impl<std::uint16_t, std::uint64_t>(op1, op2, *this);
128+
CPU_InstrImpl::__hcpu_adc_rrm_impl<std::uint16_t, std::uint64_t>(op1, op2, *this);
127129
break;
128130
case Mode::b32:
129-
impl.__hcpu_adc_rrm_impl<std::uint32_t, std::uint64_t>(op1, op2, *this);
131+
CPU_InstrImpl::__hcpu_adc_rrm_impl<std::uint32_t, std::uint64_t>(op1, op2, *this);
130132
break;
131133
case Mode::b64:
132-
impl.__hcpu_adc_rrm_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
134+
CPU_InstrImpl::__hcpu_adc_rrm_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
133135
break;
134136
}
135137
break;
@@ -144,16 +146,16 @@ void HyperCPU::CPU::ExecADC(const IInstruction& instr, OperandContainer op1, Ope
144146
/* ADC R_RM does not support different register sizes - we can call implementation directly */
145147
switch (instr.m_opcode_mode.md1) {
146148
case Mode::b8:
147-
impl.__hcpu_adc_rm_impl<std::uint8_t, std::uint64_t>(op1, op2, *this);
149+
CPU_InstrImpl::__hcpu_adc_rm_impl<std::uint8_t, std::uint64_t>(op1, op2, *this);
148150
break;
149151
case Mode::b16:
150-
impl.__hcpu_adc_rm_impl<std::uint16_t, std::uint64_t>(op1, op2, *this);
152+
CPU_InstrImpl::__hcpu_adc_rm_impl<std::uint16_t, std::uint64_t>(op1, op2, *this);
151153
break;
152154
case Mode::b32:
153-
impl.__hcpu_adc_rm_impl<std::uint32_t, std::uint64_t>(op1, op2, *this);
155+
CPU_InstrImpl::__hcpu_adc_rm_impl<std::uint32_t, std::uint64_t>(op1, op2, *this);
154156
break;
155157
case Mode::b64:
156-
impl.__hcpu_adc_rm_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
158+
CPU_InstrImpl::__hcpu_adc_rm_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
157159
break;
158160
}
159161
break;
@@ -168,16 +170,16 @@ void HyperCPU::CPU::ExecADC(const IInstruction& instr, OperandContainer op1, Ope
168170
/* ADC R_RM does not support different register sizes - we can call implementation directly */
169171
switch (instr.m_opcode_mode.md1) {
170172
case Mode::b8:
171-
impl.__hcpu_adc_rimm_impl<std::uint8_t, std::uint8_t>(op1, op2, *this);
173+
CPU_InstrImpl::__hcpu_adc_rimm_impl<std::uint8_t, std::uint8_t>(op1, op2, *this);
172174
break;
173175
case Mode::b16:
174-
impl.__hcpu_adc_rimm_impl<std::uint16_t, std::uint16_t>(op1, op2, *this);
176+
CPU_InstrImpl::__hcpu_adc_rimm_impl<std::uint16_t, std::uint16_t>(op1, op2, *this);
175177
break;
176178
case Mode::b32:
177-
impl.__hcpu_adc_rimm_impl<std::uint32_t, std::uint32_t>(op1, op2, *this);
179+
CPU_InstrImpl::__hcpu_adc_rimm_impl<std::uint32_t, std::uint32_t>(op1, op2, *this);
178180
break;
179181
case Mode::b64:
180-
impl.__hcpu_adc_rimm_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
182+
CPU_InstrImpl::__hcpu_adc_rimm_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
181183
break;
182184
}
183185
break;

‎src/Emulator/Core/CPU/InstructionsImpl/ADD.cpp‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -71,16 +71,16 @@ void HyperCPU::CPU::ExecADD(const IInstruction& instr, OperandContainer op1, Ope
7171
/* ADD R_R does not support different register sizes - we can call implementation directly */
7272
switch (instr.m_opcode_mode.md1) {
7373
case Mode::b8:
74-
impl.__hcpu_add_rr_impl<std::uint8_t, std::uint8_t>(op1, op2, *this);
74+
CPU_InstrImpl::__hcpu_add_rr_impl<std::uint8_t, std::uint8_t>(op1, op2, *this);
7575
break;
7676
case Mode::b16:
77-
impl.__hcpu_add_rr_impl<std::uint16_t, std::uint16_t>(op1, op2, *this);
77+
CPU_InstrImpl::__hcpu_add_rr_impl<std::uint16_t, std::uint16_t>(op1, op2, *this);
7878
break;
7979
case Mode::b32:
80-
impl.__hcpu_add_rr_impl<std::uint32_t, std::uint32_t>(op1, op2, *this);
80+
CPU_InstrImpl::__hcpu_add_rr_impl<std::uint32_t, std::uint32_t>(op1, op2, *this);
8181
break;
8282
case Mode::b64:
83-
impl.__hcpu_add_rr_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
83+
CPU_InstrImpl::__hcpu_add_rr_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
8484
break;
8585
}
8686
break;
@@ -95,16 +95,16 @@ void HyperCPU::CPU::ExecADD(const IInstruction& instr, OperandContainer op1, Ope
9595
/* ADD R_RM does not support different register sizes - we can call implementation directly */
9696
switch (instr.m_opcode_mode.md1) {
9797
case Mode::b8:
98-
impl.__hcpu_add_rrm_impl<std::uint8_t, std::uint64_t>(op1, op2, *this);
98+
CPU_InstrImpl::__hcpu_add_rrm_impl<std::uint8_t, std::uint64_t>(op1, op2, *this);
9999
break;
100100
case Mode::b16:
101-
impl.__hcpu_add_rrm_impl<std::uint16_t, std::uint64_t>(op1, op2, *this);
101+
CPU_InstrImpl::__hcpu_add_rrm_impl<std::uint16_t, std::uint64_t>(op1, op2, *this);
102102
break;
103103
case Mode::b32:
104-
impl.__hcpu_add_rrm_impl<std::uint32_t, std::uint64_t>(op1, op2, *this);
104+
CPU_InstrImpl::__hcpu_add_rrm_impl<std::uint32_t, std::uint64_t>(op1, op2, *this);
105105
break;
106106
case Mode::b64:
107-
impl.__hcpu_add_rrm_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
107+
CPU_InstrImpl::__hcpu_add_rrm_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
108108
break;
109109
}
110110
break;
@@ -119,16 +119,16 @@ void HyperCPU::CPU::ExecADD(const IInstruction& instr, OperandContainer op1, Ope
119119
/* ADD R_RM does not support different register sizes - we can call implementation directly */
120120
switch (instr.m_opcode_mode.md1) {
121121
case Mode::b8:
122-
impl.__hcpu_add_rm_impl<std::uint8_t, std::uint64_t>(op1, op2, *this);
122+
CPU_InstrImpl::__hcpu_add_rm_impl<std::uint8_t, std::uint64_t>(op1, op2, *this);
123123
break;
124124
case Mode::b16:
125-
impl.__hcpu_add_rm_impl<std::uint16_t, std::uint64_t>(op1, op2, *this);
125+
CPU_InstrImpl::__hcpu_add_rm_impl<std::uint16_t, std::uint64_t>(op1, op2, *this);
126126
break;
127127
case Mode::b32:
128-
impl.__hcpu_add_rm_impl<std::uint32_t, std::uint64_t>(op1, op2, *this);
128+
CPU_InstrImpl::__hcpu_add_rm_impl<std::uint32_t, std::uint64_t>(op1, op2, *this);
129129
break;
130130
case Mode::b64:
131-
impl.__hcpu_add_rm_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
131+
CPU_InstrImpl::__hcpu_add_rm_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
132132
break;
133133
}
134134
break;
@@ -143,16 +143,16 @@ void HyperCPU::CPU::ExecADD(const IInstruction& instr, OperandContainer op1, Ope
143143
/* ADD R_RM does not support different register sizes - we can call implementation directly */
144144
switch (instr.m_opcode_mode.md1) {
145145
case Mode::b8:
146-
impl.__hcpu_add_rimm_impl<std::uint8_t, std::uint8_t>(op1, op2, *this);
146+
CPU_InstrImpl::__hcpu_add_rimm_impl<std::uint8_t, std::uint8_t>(op1, op2, *this);
147147
break;
148148
case Mode::b16:
149-
impl.__hcpu_add_rimm_impl<std::uint16_t, std::uint16_t>(op1, op2, *this);
149+
CPU_InstrImpl::__hcpu_add_rimm_impl<std::uint16_t, std::uint16_t>(op1, op2, *this);
150150
break;
151151
case Mode::b32:
152-
impl.__hcpu_add_rimm_impl<std::uint32_t, std::uint32_t>(op1, op2, *this);
152+
CPU_InstrImpl::__hcpu_add_rimm_impl<std::uint32_t, std::uint32_t>(op1, op2, *this);
153153
break;
154154
case Mode::b64:
155-
impl.__hcpu_add_rimm_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
155+
CPU_InstrImpl::__hcpu_add_rimm_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
156156
break;
157157
}
158158
break;

‎src/Emulator/Core/CPU/InstructionsImpl/AND.cpp‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
1818
static constexpr void __hcpu_and_rr_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
1919
static_assert(std::is_same_v<T1, T2>); // Locked by current CPU specification
2020

21-
op1.deref<T1>() = HyperALU::__hcpu_and(op1.deref<T1>(), HyperCPU::bit_cast_from<T2>(op2.ptr<T2>()));
21+
op1.deref<T1>() = HyperALU::__hcpu_and<T1>(op1.deref<T1>(), HyperCPU::bit_cast_from<T2>(op2.ptr<T2>()));
2222
}
2323

2424
/* R_RM implementation */
@@ -29,7 +29,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
2929
T2 ptr = HyperCPU::bit_cast_from<T2>(op2.ptr<T2>());
3030
T1 val = cpu.mem_controller->Read<T1>(ptr);
3131

32-
op1.deref<T1>() = HyperALU::__hcpu_and(op1.deref<T1>(), val);
32+
op1.deref<T1>() = HyperALU::__hcpu_and<T1>(op1.deref<T1>(), val);
3333
}
3434

3535
/* R_M implementation */
@@ -40,7 +40,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
4040
T2 ptr = HyperCPU::bit_cast<T2>(op2);
4141
T1 val = cpu.mem_controller->Read<T1>(ptr);
4242

43-
op1.deref<T1>() = HyperALU::__hcpu_and(op1.deref<T1>(), val);
43+
op1.deref<T1>() = HyperALU::__hcpu_and<T1>(op1.deref<T1>(), val);
4444
}
4545

4646
/* R_IMM implementation */
@@ -50,7 +50,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
5050

5151
T1 val = HyperCPU::bit_cast<T1>(op2);
5252

53-
op1.deref<T1>() = HyperALU::__hcpu_and(op1.deref<T1>(), val);
53+
op1.deref<T1>() = HyperALU::__hcpu_and<T1>(op1.deref<T1>(), val);
5454
}
5555
};
5656

@@ -67,16 +67,16 @@ void HyperCPU::CPU::ExecAND(const IInstruction& instr, OperandContainer op1, Ope
6767
/* AND R_R does not support different register sizes - we can call implementation directly */
6868
switch (instr.m_opcode_mode.md1) {
6969
case Mode::b8:
70-
impl.__hcpu_and_rr_impl<std::uint8_t, std::uint8_t>(op1, op2, *this);
70+
CPU_InstrImpl::__hcpu_and_rr_impl<std::uint8_t, std::uint8_t>(op1, op2, *this);
7171
break;
7272
case Mode::b16:
73-
impl.__hcpu_and_rr_impl<std::uint16_t, std::uint16_t>(op1, op2, *this);
73+
CPU_InstrImpl::__hcpu_and_rr_impl<std::uint16_t, std::uint16_t>(op1, op2, *this);
7474
break;
7575
case Mode::b32:
76-
impl.__hcpu_and_rr_impl<std::uint32_t, std::uint32_t>(op1, op2, *this);
76+
CPU_InstrImpl::__hcpu_and_rr_impl<std::uint32_t, std::uint32_t>(op1, op2, *this);
7777
break;
7878
case Mode::b64:
79-
impl.__hcpu_and_rr_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
79+
CPU_InstrImpl::__hcpu_and_rr_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
8080
break;
8181
}
8282
break;
@@ -91,16 +91,16 @@ void HyperCPU::CPU::ExecAND(const IInstruction& instr, OperandContainer op1, Ope
9191
/* AND R_RM does not support different register sizes - we can call implementation directly */
9292
switch (instr.m_opcode_mode.md1) {
9393
case Mode::b8:
94-
impl.__hcpu_and_rrm_impl<std::uint8_t, std::uint64_t>(op1, op2, *this);
94+
CPU_InstrImpl::__hcpu_and_rrm_impl<std::uint8_t, std::uint64_t>(op1, op2, *this);
9595
break;
9696
case Mode::b16:
97-
impl.__hcpu_and_rrm_impl<std::uint16_t, std::uint64_t>(op1, op2, *this);
97+
CPU_InstrImpl::__hcpu_and_rrm_impl<std::uint16_t, std::uint64_t>(op1, op2, *this);
9898
break;
9999
case Mode::b32:
100-
impl.__hcpu_and_rrm_impl<std::uint32_t, std::uint64_t>(op1, op2, *this);
100+
CPU_InstrImpl::__hcpu_and_rrm_impl<std::uint32_t, std::uint64_t>(op1, op2, *this);
101101
break;
102102
case Mode::b64:
103-
impl.__hcpu_and_rrm_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
103+
CPU_InstrImpl::__hcpu_and_rrm_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
104104
break;
105105
}
106106
break;
@@ -115,16 +115,16 @@ void HyperCPU::CPU::ExecAND(const IInstruction& instr, OperandContainer op1, Ope
115115
/* AND R_RM does not support different register sizes - we can call implementation directly */
116116
switch (instr.m_opcode_mode.md1) {
117117
case Mode::b8:
118-
impl.__hcpu_and_rm_impl<std::uint8_t, std::uint64_t>(op1, op2, *this);
118+
CPU_InstrImpl::__hcpu_and_rm_impl<std::uint8_t, std::uint64_t>(op1, op2, *this);
119119
break;
120120
case Mode::b16:
121-
impl.__hcpu_and_rm_impl<std::uint16_t, std::uint64_t>(op1, op2, *this);
121+
CPU_InstrImpl::__hcpu_and_rm_impl<std::uint16_t, std::uint64_t>(op1, op2, *this);
122122
break;
123123
case Mode::b32:
124-
impl.__hcpu_and_rm_impl<std::uint32_t, std::uint64_t>(op1, op2, *this);
124+
CPU_InstrImpl::__hcpu_and_rm_impl<std::uint32_t, std::uint64_t>(op1, op2, *this);
125125
break;
126126
case Mode::b64:
127-
impl.__hcpu_and_rm_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
127+
CPU_InstrImpl::__hcpu_and_rm_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
128128
break;
129129
}
130130
break;
@@ -139,16 +139,16 @@ void HyperCPU::CPU::ExecAND(const IInstruction& instr, OperandContainer op1, Ope
139139
/* AND R_RM does not support different register sizes - we can call implementation directly */
140140
switch (instr.m_opcode_mode.md1) {
141141
case Mode::b8:
142-
impl.__hcpu_and_rimm_impl<std::uint8_t, std::uint8_t>(op1, op2, *this);
142+
CPU_InstrImpl::__hcpu_and_rimm_impl<std::uint8_t, std::uint8_t>(op1, op2, *this);
143143
break;
144144
case Mode::b16:
145-
impl.__hcpu_and_rimm_impl<std::uint16_t, std::uint16_t>(op1, op2, *this);
145+
CPU_InstrImpl::__hcpu_and_rimm_impl<std::uint16_t, std::uint16_t>(op1, op2, *this);
146146
break;
147147
case Mode::b32:
148-
impl.__hcpu_and_rimm_impl<std::uint32_t, std::uint32_t>(op1, op2, *this);
148+
CPU_InstrImpl::__hcpu_and_rimm_impl<std::uint32_t, std::uint32_t>(op1, op2, *this);
149149
break;
150150
case Mode::b64:
151-
impl.__hcpu_and_rimm_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
151+
CPU_InstrImpl::__hcpu_and_rimm_impl<std::uint64_t, std::uint64_t>(op1, op2, *this);
152152
break;
153153
}
154154
break;

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