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Update LODSB, STDSB, MOV and MUL instructions
1 parent bdfeba0 commit 77d1aa3

7 files changed

Lines changed: 266 additions & 188 deletions

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‎src/Emulator/Core/CPU/InstructionsImpl/ADD.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
1919
static_assert(std::is_same_v<T1, T2>); // Locked by current CPU specification
2020

2121
cpu.ovf = AdditionWillOverflow(op1.deref<T1>(), op2.deref<T2>());
22-
op1.deref<T1>() = HyperALU::__hcpu_add(op1.deref<T1>(), HyperCPU::bit_cast_from<T2>(op2.ptr<T2>()));
22+
op1.deref<T1>() = HyperALU::__hcpu_add<T1>(op1.deref<T1>(), HyperCPU::bit_cast_from<T1>(op2.ptr<T2>()));
2323
}
2424

2525
/* R_RM implementation */
@@ -31,7 +31,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
3131
T1 val = cpu.mem_controller->Read<T1>(ptr);
3232
cpu.ovf = AdditionWillOverflow(op1.deref<T1>(), val);
3333

34-
op1.deref<T1>() = HyperALU::__hcpu_add(op1.deref<T1>(), val);
34+
op1.deref<T1>() = HyperALU::__hcpu_add<T1>(op1.deref<T1>(), val);
3535
}
3636

3737
/* R_M implementation */
@@ -43,7 +43,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
4343
T1 val = cpu.mem_controller->Read<T1>(ptr);
4444
cpu.ovf = AdditionWillOverflow(op1.deref<T1>(), val);
4545

46-
op1.deref<T1>() = HyperALU::__hcpu_add(op1.deref<T1>(), val);
46+
op1.deref<T1>() = HyperALU::__hcpu_add<T1>(op1.deref<T1>(), val);
4747
}
4848

4949
/* R_IMM implementation */
@@ -54,7 +54,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
5454
T1 val = HyperCPU::bit_cast<T1>(op2);
5555
cpu.ovf = AdditionWillOverflow(op1.deref<T1>(), val);
5656

57-
op1.deref<T1>() = HyperALU::__hcpu_add(op1.deref<T1>(), val);
57+
op1.deref<T1>() = HyperALU::__hcpu_add<T1>(op1.deref<T1>(), val);
5858
}
5959
};
6060

‎src/Emulator/Core/CPU/InstructionsImpl/CMP.cpp‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -12,9 +12,9 @@ class HyperCPU::CPU::CPU_InstrImpl {
1212
static constexpr T3 __hcpu_cmp_rr_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& /* cpu */) {
1313
static_assert(std::is_same_v<T1, T2>); // Locked by current CPU specification
1414

15-
return HyperALU::__hcpu_cmp(
15+
return HyperALU::__hcpu_cmp<T1>(
1616
HyperCPU::bit_cast_from<T1>(op1.ptr<T1>()),
17-
HyperCPU::bit_cast_from<T2>(op2.ptr<T2>())
17+
HyperCPU::bit_cast_from<T1>(op2.ptr<T2>())
1818
);
1919
}
2020

@@ -26,7 +26,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
2626
std::uint64_t ptr;
2727
std::memcpy(&ptr, op2.ptr<void>(), sizeof(ptr));
2828

29-
return HyperALU::__hcpu_cmp(
29+
return HyperALU::__hcpu_cmp<T1>(
3030
HyperCPU::bit_cast_from<T1>(op1.ptr<T1>()),
3131
cpu.mem_controller->Read<T1>(ptr)
3232
);
@@ -37,7 +37,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
3737
static constexpr T3 __hcpu_cmp_rm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
3838
static_assert(std::is_same_v<T2, std::uint64_t>); // Locked by current CPU specification
3939

40-
return HyperALU::__hcpu_cmp(
40+
return HyperALU::__hcpu_cmp<T1>(
4141
HyperCPU::bit_cast_from<T1>(op1.ptr<T1>()),
4242
cpu.mem_controller->Read<T1>(op2)
4343
);
@@ -48,7 +48,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
4848
static constexpr T3 __hcpu_cmp_rimm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& /* cpu */) {
4949
static_assert(std::is_same_v<T1, T2>); // Locked by current CPU specification
5050

51-
return HyperALU::__hcpu_cmp(
51+
return HyperALU::__hcpu_cmp<T1>(
5252
HyperCPU::bit_cast_from<T1>(op1.ptr<T1>()),
5353
HyperCPU::bit_cast<T1>(op2)
5454
);
@@ -59,9 +59,9 @@ class HyperCPU::CPU::CPU_InstrImpl {
5959
static constexpr T3 __hcpu_cmp_rmm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
6060
static_assert(std::is_same_v<T1, T2>); // Locked by current CPU specification
6161

62-
return HyperALU::__hcpu_cmp(
62+
return HyperALU::__hcpu_cmp<T1>(
6363
cpu.mem_controller->Read<T1>(op1.deref<std::uint64_t>()),
64-
cpu.mem_controller->Read<T2>(HyperCPU::bit_cast<T2>(op2))
64+
cpu.mem_controller->Read<T1>(HyperCPU::bit_cast<T2>(op2))
6565
);
6666
}
6767

@@ -70,7 +70,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
7070
static constexpr T3 __hcpu_cmp_rmr_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
7171
static_assert(std::is_same_v<T1, std::uint64_t>); // Locked by current CPU specification
7272

73-
return HyperALU::__hcpu_cmp(
73+
return HyperALU::__hcpu_cmp<T2>(
7474
cpu.mem_controller->Read<T2>(op1.deref<T1>()),
7575
op2.deref<T2>()
7676
);
@@ -81,7 +81,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
8181
static constexpr T3 __hcpu_cmp_rmimm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
8282
static_assert(std::is_same_v<T1, std::uint64_t>); // Locked by current CPU specification
8383

84-
return HyperALU::__hcpu_cmp(
84+
return HyperALU::__hcpu_cmp<T2>(
8585
cpu.mem_controller->Read<T2>(op1.deref<T1>()),
8686
HyperCPU::bit_cast<T2>(op2)
8787
);
@@ -92,7 +92,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
9292
static constexpr T3 __hcpu_cmp_mr_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
9393
static_assert(std::is_same_v<T1, std::uint64_t>); // Locked by current CPU specification
9494

95-
return HyperALU::__hcpu_cmp(
95+
return HyperALU::__hcpu_cmp<T2>(
9696
cpu.mem_controller->Read<T2>(HyperCPU::bit_cast<T1>(op1)),
9797
op2.deref<T2>()
9898
);

‎src/Emulator/Core/CPU/InstructionsImpl/LODSB.cpp‎

Lines changed: 32 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,36 +1,50 @@
11
#include "Emulator/Core/CPU/ALU.hpp"
22
#include "Emulator/Core/CPU/CPU.hpp"
33

4-
using namespace HyperALU;
4+
class HyperCPU::CPU::CPU_InstrImpl {
5+
constexpr CPU_InstrImpl() { }
6+
7+
template<typename T1, typename T2>
8+
static constexpr void __hcpu_lodsb_rimm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
9+
T1 value = cpu.mem_controller->Read(cpu.xbp + HyperCPU::bit_cast<T2>(op2));
10+
op1.deref<T1>() = value;
11+
}
12+
};
13+
14+
template<typename T1, typename TImpl>
15+
[[gnu::always_inline]]
16+
void ResolveOP2Mode(HyperCPU::Mode md2, HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, HyperCPU::CPU& cpu) {
17+
TImpl impl;
18+
19+
switch (md2) {
20+
case HyperCPU::Mode::b8: impl.template __hcpu_lodsb_rimm_impl<T1, std::int8_t>(op1, op2, cpu); break;
21+
case HyperCPU::Mode::b16: impl.template __hcpu_lodsb_rimm_impl<T1, std::int16_t>(op1, op2, cpu); break;
22+
case HyperCPU::Mode::b32: impl.template __hcpu_lodsb_rimm_impl<T1, std::int32_t>(op1, op2, cpu); break;
23+
case HyperCPU::Mode::b64: impl.template __hcpu_lodsb_rimm_impl<T1, std::int64_t>(op1, op2, cpu); break;
24+
default: std::abort();
25+
}
26+
}
527

628
void HyperCPU::CPU::ExecLODSB(const IInstruction& instr, OperandContainer op1, OperandContainer op2) {
729
switch (instr.m_op_types) {
830
case OperandTypes::R_IMM: {
9-
switch (instr.m_opcode_mode) {
10-
case Mode::b8: {
11-
std::uint8_t val = HyperCPU::bit_cast<std::uint8_t>(op2);
12-
op1.deref<std::uint8_t>() = __hcpu_or(op1.deref<std::uint8_t>(), val);
31+
switch (instr.m_opcode_mode.md1) {
32+
case Mode::b8:
33+
ResolveOP2Mode<std::uint8_t, CPU_InstrImpl>(instr.m_opcode_mode.md2, op1, op2, *this);
1334
break;
14-
}
1535

16-
case Mode::b16: {
17-
std::uint16_t val = HyperCPU::bit_cast<std::uint16_t>(op2);
18-
op1.deref<std::uint16_t>() = __hcpu_or(op1.deref<std::uint16_t>(), val);
36+
case Mode::b16:
37+
ResolveOP2Mode<std::uint16_t, CPU_InstrImpl>(instr.m_opcode_mode.md2, op1, op2, *this);
1938
break;
20-
}
2139

22-
case Mode::b32: {
23-
std::uint32_t val = HyperCPU::bit_cast<std::uint32_t>(op2);
24-
op1.deref<std::uint32_t>() = __hcpu_or(op1.deref<std::uint32_t>(), val);
40+
case Mode::b32:
41+
ResolveOP2Mode<std::uint32_t, CPU_InstrImpl>(instr.m_opcode_mode.md2, op1, op2, *this);
2542
break;
26-
}
2743

28-
case Mode::b64: {
29-
std::uint64_t val = HyperCPU::bit_cast<std::uint64_t>(op2);
30-
op1.deref<std::uint64_t>() = __hcpu_or(op1.deref<std::uint64_t>(), val);
44+
case Mode::b64:
45+
ResolveOP2Mode<std::uint64_t, CPU_InstrImpl>(instr.m_opcode_mode.md2, op1, op2, *this);
3146
break;
3247
}
33-
}
3448
break;
3549
}
3650

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