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Partial CMP reimplementation
1 parent 04db26a commit bc17fdf

6 files changed

Lines changed: 67 additions & 22 deletions

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‎src/Emulator/Core/CPU/InstructionsImpl/ADC.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
2727

2828
/* R_RM implementation */
2929
template<typename T1, typename T2>
30-
void __hcpu_adc_rrm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
30+
static constexpr void __hcpu_adc_rrm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
3131
static_assert(std::is_same_v<T2, std::uint64_t>); // Locked by current CPU specification
3232

3333
T2 ptr = HyperCPU::bit_cast_from<T2>(op2.ptr<T2>());
@@ -42,7 +42,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
4242

4343
/* R_M implementation */
4444
template<typename T1, typename T2>
45-
void __hcpu_adc_rm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
45+
static constexpr void __hcpu_adc_rm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
4646
static_assert(std::is_same_v<T2, std::uint64_t>); // Locked by current CPU specification
4747

4848
T2 ptr = HyperCPU::bit_cast<T2>(op2);
@@ -57,7 +57,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
5757

5858
/* R_IMM implementation */
5959
template<typename T1, typename T2>
60-
void __hcpu_adc_rimm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
60+
static constexpr void __hcpu_adc_rimm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
6161
static_assert(std::is_same_v<T1, T2>); // Locked by current CPU specification
6262

6363
T1 val = HyperCPU::bit_cast<T1>(op2);

‎src/Emulator/Core/CPU/InstructionsImpl/ADD.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
2424

2525
/* R_RM implementation */
2626
template<typename T1, typename T2>
27-
void __hcpu_add_rrm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
27+
static constexpr void __hcpu_add_rrm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
2828
static_assert(std::is_same_v<T2, std::uint64_t>); // Locked by current CPU specification
2929

3030
T2 ptr = HyperCPU::bit_cast_from<T2>(op2.ptr<T2>());
@@ -36,7 +36,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
3636

3737
/* R_M implementation */
3838
template<typename T1, typename T2>
39-
void __hcpu_add_rm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
39+
static constexpr void __hcpu_add_rm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
4040
static_assert(std::is_same_v<T2, std::uint64_t>); // Locked by current CPU specification
4141

4242
T2 ptr = HyperCPU::bit_cast<T2>(op2);
@@ -48,12 +48,12 @@ class HyperCPU::CPU::CPU_InstrImpl {
4848

4949
/* R_IMM implementation */
5050
template<typename T1, typename T2>
51-
void __hcpu_add_rimm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
51+
static constexpr void __hcpu_add_rimm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
5252
static_assert(std::is_same_v<T1, T2>); // Locked by current CPU specification
5353

5454
T1 val = HyperCPU::bit_cast<T1>(op2);
5555
cpu.ovf = AdditionWillOverflow(op1.deref<T1>(), val);
56-
56+
5757
op1.deref<T1>() = HyperALU::__hcpu_add(op1.deref<T1>(), val);
5858
}
5959
};

‎src/Emulator/Core/CPU/InstructionsImpl/AND.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
2323

2424
/* R_RM implementation */
2525
template<typename T1, typename T2>
26-
void __hcpu_and_rrm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
26+
static constexpr void __hcpu_and_rrm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
2727
static_assert(std::is_same_v<T2, std::uint64_t>); // Locked by current CPU specification
2828

2929
T2 ptr = HyperCPU::bit_cast_from<T2>(op2.ptr<T2>());
@@ -34,7 +34,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
3434

3535
/* R_M implementation */
3636
template<typename T1, typename T2>
37-
void __hcpu_and_rm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
37+
static constexpr void __hcpu_and_rm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
3838
static_assert(std::is_same_v<T2, std::uint64_t>); // Locked by current CPU specification
3939

4040
T2 ptr = HyperCPU::bit_cast<T2>(op2);
@@ -45,11 +45,11 @@ class HyperCPU::CPU::CPU_InstrImpl {
4545

4646
/* R_IMM implementation */
4747
template<typename T1, typename T2>
48-
void __hcpu_and_rimm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
48+
static constexpr void __hcpu_and_rimm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
4949
static_assert(std::is_same_v<T1, T2>); // Locked by current CPU specification
5050

5151
T1 val = HyperCPU::bit_cast<T1>(op2);
52-
52+
5353
op1.deref<T1>() = HyperALU::__hcpu_and(op1.deref<T1>(), val);
5454
}
5555
};

‎src/Emulator/Core/CPU/InstructionsImpl/ANDN.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
2424

2525
/* R_RM implementation */
2626
template<typename T1, typename T2>
27-
void __hcpu_andn_rrm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
27+
static constexpr void __hcpu_andn_rrm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
2828
static_assert(std::is_same_v<T2, std::uint64_t>); // Locked by current CPU specification
2929

3030
T2 ptr = HyperCPU::bit_cast_from<T2>(op2.ptr<T2>());
@@ -36,7 +36,7 @@ class HyperCPU::CPU::CPU_InstrImpl {
3636

3737
/* R_M implementation */
3838
template<typename T1, typename T2>
39-
void __hcpu_andn_rm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
39+
static constexpr void __hcpu_andn_rm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
4040
static_assert(std::is_same_v<T2, std::uint64_t>); // Locked by current CPU specification
4141

4242
T2 ptr = HyperCPU::bit_cast<T2>(op2);
@@ -48,12 +48,12 @@ class HyperCPU::CPU::CPU_InstrImpl {
4848

4949
/* R_IMM implementation */
5050
template<typename T1, typename T2>
51-
void __hcpu_andn_rimm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
51+
static constexpr void __hcpu_andn_rimm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
5252
static_assert(std::is_same_v<T1, T2>); // Locked by current CPU specification
5353

5454
T1 val = HyperCPU::bit_cast<T1>(op2);
5555
cpu.ovf = AdditionWillOverflow(op1.deref<T1>(), val);
56-
56+
5757
op1.deref<T1>() = HyperALU::__hcpu_and(HyperALU::__hcpu_not(op1.deref<T1>()), val);
5858
}
5959
};

‎src/Emulator/Core/CPU/InstructionsImpl/BSWAP.cpp‎

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -3,25 +3,22 @@
33
#include "Emulator/Misc/byteswap.hpp"
44

55
void HyperCPU::CPU::ExecBSWAP(const IInstruction& instr, OperandContainer op1, OperandContainer /* op2 */) {
6-
switch (instr.m_opcode_mode) {
6+
switch (instr.m_opcode_mode.md1) {
77
case Mode::b8:
88
break;
99

1010
case Mode::b16: {
11-
auto& dst = op1.deref<std::uint16_t>();
12-
dst = HyperCPU::byteswap(dst);
11+
dst = HyperCPU::byteswap(op1.deref<std::uint16_t>());
1312
break;
1413
}
1514

1615
case Mode::b32: {
17-
auto& dst = op1.deref<std::uint32_t>();
18-
dst = HyperCPU::byteswap(dst);
16+
dst = HyperCPU::byteswap(op1.deref<std::uint32_t>());
1917
break;
2018
}
2119

2220
case Mode::b64: {
23-
auto& dst = op1.deref<std::uint64_t>();
24-
dst = HyperCPU::byteswap(dst);
21+
dst = HyperCPU::byteswap(op1.deref<std::uint64_t>());
2522
break;
2623
}
2724
}

‎src/Emulator/Core/CPU/InstructionsImpl/CMP.cpp‎

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,54 @@
33

44
#include "Emulator/Misc/bit_cast.hpp"
55

6+
class HyperCPU::CPU::CPU_InstrImpl {
7+
public:
8+
constexpr CPU_InstrImpl() { }
9+
10+
/* R_R implementation */
11+
template<typename T1, typename T2, typename T3>
12+
static constexpr T3 __hcpu_cmp_rr_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
13+
static_assert(std::is_same_v<T1, T2>); // Locked by current CPU specification
14+
15+
return HyperALU::__hcpu_cmp(
16+
HyperCPU::bit_cast_from<T1>(op1.ptr<T1>()),
17+
HyperCPU::bit_cast_from<T2>(op2.ptr<T2>())
18+
);
19+
}
20+
21+
/* R_RM implementation */
22+
template<typename T1, typename T2, typename T3>
23+
static constexpr T3 __hcpu_cmp_rrm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
24+
static_assert(std::is_same_v<T2, std::uint64_t>); // Locked by current CPU specification
25+
26+
return HyperALU::__hcpu_cmp(
27+
HyperCPU::bit_cast_from<T1>(op1.ptr<T1>()),
28+
HyperCPU::bit_cast_from<T2>(op2.ptr<T2>())
29+
);
30+
}
31+
32+
/* R_M implementation */
33+
template<typename T1, typename T2, typename T3>
34+
static constexpr T3 __hcpu_cmp_rm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
35+
static_assert(std::is_same_v<T2, std::uint64_t>); // Locked by current CPU specification
36+
37+
T2 ptr = HyperCPU::bit_cast<T2>(op2);
38+
T1 val = cpu.mem_controller->Read8(ptr);
39+
40+
op1.deref<T1>() = HyperALU::__hcpu_and(op1.deref<T1>(), val);
41+
}
42+
43+
/* R_IMM implementation */
44+
template<typename T1, typename T2, typename T3>
45+
static constexpr T3 __hcpu_cmp_rimm_impl(HyperCPU::OperandContainer& op1, HyperCPU::OperandContainer& op2, CPU& cpu) {
46+
static_assert(std::is_same_v<T1, T2>); // Locked by current CPU specification
47+
48+
T1 val = HyperCPU::bit_cast<T1>(op2);
49+
50+
op1.deref<T1>() = HyperALU::__hcpu_and(op1.deref<T1>(), val);
51+
}
52+
};
53+
654
void HyperCPU::CPU::ExecCMP(const IInstruction& instr, OperandContainer op1, OperandContainer op2) {
755
std::int8_t res = 0;
856
switch (instr.m_op_types) {

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